106 lines
3.1 KiB
C
106 lines
3.1 KiB
C
/* i82378.h - i82378 IBC (ISA Bridge Controller) driver */
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/* Copyright 1984-1996 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01c,30oct96,tam added IBC_READ_BYTE and IBC_WRITE_BYTE definitions (spr #7415).
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01b,11oct96,tam added _ASMLANGUAGE conditional.
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01a,29jan96,tam written.
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*/
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#ifndef __INCi82378Ibch
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#define __INCi82378Ibch
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* The macro IBC_BASE_ADRS, PIC_REG_ADDR_INTERVAL & PIT_REG_ADDR_INTERVAL
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* must be defined when including this header.
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*/
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/* default definitions */
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#define CAST
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#define PIC_ADRS(base,reg) (CAST (base+(reg*PIC_REG_ADDR_INTERVAL)))
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/* register definitions */
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#define PIC_port1(base) PIC_ADRS(base,0x00) /* port 1. */
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#define PIC_port2(base) PIC_ADRS(base,0x01) /* port 2. */
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/* hardware register access macros */
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#ifndef IBC_BYTE_READ /* reads IBC register */
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# define IBC_BYTE_READ(addr,pData) (*pData = *(UCHAR *)(addr))
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#endif
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#ifndef IBC_BYTE_WRITE /* write to IBC register */
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# define IBC_BYTE_WRITE(addr,data) *(UCHAR *)(addr) = (data); EIEIO
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#endif
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/* alias */
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#define PIC_IMASK(base) PIC_port2(base) /* Interrupt mask. */
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#define PIC_IACK(base) PIC_port1(base) /* Interrupt acknowledge. */
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#define PIC_ISR_MASK(base) PIC_port1(base) /* in-service register mask */
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#define PIC_IRR_MASK(base) PIC_port1(base) /* interrupt request reg */
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#define OCW3_DEF 0x08 /* 3rd default control word */
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#define OCW3_PCB 0x04 /* Polling Control Bit */
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#define OCW3_ISR 0x03 /* Read in-service reg */
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#define OCW3_IRR 0x02 /* Read inter request reg */
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#define ISA_INTR_ACK_REG (CPU_PCI_IACK_ADRS + 0x1ff0)
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#define i82378_INT1_CTRL (IBC_BASE_ADRS + 0x0020) /* pic1 82378 */
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#define i82378_INT1_MASK (IBC_BASE_ADRS + 0x0021)
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#define i82378_INT1_ELC (IBC_BASE_ADRS + 0x04d0)
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#define i82378_INT2_CTRL (IBC_BASE_ADRS + 0x00a0) /* pic2 82378 */
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#define i82378_INT2_MASK (IBC_BASE_ADRS + 0x00a1)
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#define i82378_INT2_ELC (IBC_BASE_ADRS + 0x04d1)
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#define i82378_TMR1_CNT0 (IBC_BASE_ADRS + 0x0040) /* timer */
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#define i82378_TMR1_CNT1 (IBC_BASE_ADRS + 0x0041)
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#define i82378_TMR1_CNT2 (IBC_BASE_ADRS + 0x0042)
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#define i82378_TMR1_CMOD (IBC_BASE_ADRS + 0x0043)
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#define i82378_RST_IRQ12 (IBC_BASE_ADRS + 0x0060)
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#define i82378_NMI_SCTRL (IBC_BASE_ADRS + 0x0061)
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#define i82378_PCOP (IBC_BASE_ADRS + 0x0c04)
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#define i82378_TMCP (IBC_BASE_ADRS + 0x0c01)
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/* programmable interrupt controller (PIC) */
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#define PIC1_BASE_ADR i82378_INT1_CTRL
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#define PIC2_BASE_ADR i82378_INT2_CTRL
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/* programmable interrupt timers */
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#define PIT_BASE_ADR i82378_TMR1_CNT0 /* timeraddrs */
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#define PIT_CLOCK 1193180
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/* typedefs */
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#ifndef _ASMLANGUAGE
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typedef struct intHandlerDesc /* interrupt handler desciption */
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{
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VOIDFUNCPTR vec; /* interrupt vector */
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int arg; /* interrupt handler argument */
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struct intHandlerDesc * next; /* next interrupt handler & argument */
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} INT_HANDLER_DESC;
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCi82378Ibch */
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