213 lines
7.0 KiB
C
213 lines
7.0 KiB
C
/* rm9000x2glSio.h - rm9000x2gl DUART header file */
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/* Copyright 2005, 2010 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01c,29apr10,pad Moved extern C statement after include statements.
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01b,13apr05,rlg fix for misplacement of assembly if def, discoverd in build of bootroms
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01a,05apr05,rlg created for rm9000x2gl (yosemite). Created from the
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wind river ns16552Sio.h file, version 01f,07sep04.
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*/
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#ifndef __INCrm9000x2glSioh
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#define __INCrm9000x2glSioh
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/*
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*********************************************************************
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* Copyright (c) 1990,1991 Intel Corporation
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*
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* Intel hereby grants you permission to copy, modify, and
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* distribute this software and its documentation. Intel grants
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* this permission provided that the above copyright notice
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* appears in all copies and that both the copyright notice and
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* this permission notice appear in supporting documentation. In
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* addition, Intel grants this permission provided that you
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* prominently mark as not part of the original any modifications
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* made to this software or documentation, and that the name of
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* Intel Corporation not be used in advertising or publicity
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* pertaining to distribution of the software or the documentation
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* without specific, written prior permission.
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*
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* Intel Corporation does not warrant, guarantee or make any
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* representations regarding the use of, or the results of the use
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* of, the software and documentation in terms of correctness,
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* accuracy, reliability, currentness, or otherwise; and you rely
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* on the software, documentation and results solely at your own risk.
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*
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*\NOMANUAL
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**********************************************************************
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*/
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/*
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******************************************************************************
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*
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* REGISTER DESCRIPTION OF RM9000x2gl DUART
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*
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* $Id: rm9000x2gl.h,v 1.0 1993/06/07 15:07:59 wise active $
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*
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*\NOMANUAL
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*******************************************************************************
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*/
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/* Register offsets from base address */
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#define RBR 0x08 /* receiver buffer register */
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#define THR 0x0C /* transmit holding register */
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#define DLL 0x10 /* divisor latch */
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#define IER 0x14 /* interrupt enable register */
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#define DLM 0x18 /* divisor latch(MS) */
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#define IIR 0x1C /* interrupt identification register */
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#define FCR 0x20 /* FIFO control register */
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#define LCR 0x24 /* line control register */
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#define MCR 0x28 /* modem control register */
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#define LSR 0x2C /* line status register */
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#define MSR 0x30 /* modem status register */
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#define SCR 0x34 /* scratch register */
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#define BAUD_LO(baud) ((XTAL/(16*baud)) & 0xff)
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#define BAUD_HI(baud) (((XTAL/(16*baud)) & 0xff00) >> 8)
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/* Line Control Register */
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#define CHAR_LEN_5 0x00 /* 5bits data size */
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#define CHAR_LEN_6 0x01 /* 6bits data size */
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#define CHAR_LEN_7 0x02 /* 7bits data size */
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#define CHAR_LEN_8 0x03 /* 8bits data size */
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#define LCR_STB 0x04 /* 2 stop bits */
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#define ONE_STOP 0x00 /* one stop bit */
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#define LCR_PEN 0x08 /* parity enable */
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#define PARITY_NONE 0x00 /* parity disable */
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#define LCR_EPS 0x10 /* even parity select */
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#define LCR_SP 0x20 /* stick parity select */
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#define LCR_SBRK 0x40 /* break control bit */
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#define LCR_DLAB 0x80 /* divisor latch access enable */
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#define DLAB LCR_DLAB
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/* Line Status Register */
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#define LSR_DR 0x01 /* data ready */
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#define RxCHAR_AVAIL LSR_DR /* data ready */
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#define LSR_OE 0x02 /* overrun error */
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#define LSR_PE 0x04 /* parity error */
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#define LSR_FE 0x08 /* framing error */
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#define LSR_BI 0x10 /* break interrupt */
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#define LSR_THRE 0x20 /* transmit holding register empty */
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#define LSR_TEMT 0x40 /* transmitter empty */
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#define LSR_FERR 0x80 /* in fifo mode, set when PE,FE or BI error */
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/* Interrupt Identification Register */
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#define IIR_IP 0x01
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#define IIR_ID 0x0e
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#define IIR_RLS 0x06 /* received line status */
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#define Rx_INT IIR_RLS /* received line status */
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#define IIR_RDA 0x04 /* received data available */
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#define RxFIFO_INT IIR_RDA /* received data available */
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#define IIR_THRE 0x02 /* transmit holding register empty */
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#define TxFIFO_INT IIR_THRE
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#define IIR_MSTAT 0x00 /* modem status */
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#define IIR_TIMEOUT 0x0c /* char receive timeout */
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/* Interrupt Enable Register */
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#define IER_ERDAI 0x01 /* received data avail. & timeout int */
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#define RxFIFO_BIT IER_ERDAI
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#define IER_ETHREI 0x02 /* transmitter holding register empty int */
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#define TxFIFO_BIT IER_ETHREI
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#define IER_ELSI 0x04 /* receiver line status int enable */
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#define Rx_BIT IER_ELSI
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#define IER_EMSI 0x08 /* modem status int enable */
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/* Modem Control Register */
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#define MCR_DTR 0x01 /* dtr output */
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#define DTR MCR_DTR
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#define MCR_RTS 0x02 /* rts output */
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#define MCR_OUT1 0x04 /* output #1 */
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#define MCR_OUT2 0x08 /* output #2 */
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#define MCR_LOOP 0x10 /* loopback enable */
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/* Modem Status Register */
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#define MSR_DCTS 0x01 /* cts change */
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#define MSR_DDSR 0x02 /* dsr change */
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#define MSR_TERI 0x04 /* ring indicator change */
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#define MSR_DDCD 0x08 /* data carrier indicator change */
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#define MSR_CTS 0x10 /* complement of cts */
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#define MSR_DSR 0x20 /* complement of dsr */
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#define MSR_RI 0x40 /* complement of ring signal */
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#define MSR_DCD 0x80 /* complement of dcd */
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/* FIFO Control Register */
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#define FCR_EN 0x01 /* enable xmit and rcvr */
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#define FIFO_ENABLE FCR_EN
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#define FCR_RXCLR 0x02 /* clears rcvr fifo */
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#define RxCLEAR FCR_RXCLR
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#define FCR_TXCLR 0x04 /* clears xmit fifo */
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#define TxCLEAR FCR_TXCLR
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#define FCR_DMA 0x08 /* dma */
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#define FCR_RXTRIG_L 0x40 /* rcvr fifo trigger lvl low */
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#define FCR_RXTRIG_H 0x80 /* rcvr fifo trigger lvl high */
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#ifndef _ASMLANGUAGE
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#include "sioLib.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct /* RM9000x2gl_CHAN * */
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{
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/* always goes first */
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SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */
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/* callbacks */
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STATUS (*getTxChar) (); /* pointer to xmitr function */
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STATUS (*putRcvChar) (); /* pointer to rcvr function */
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void * getTxArg;
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void * putRcvArg;
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UINT8 *regs; /* RM9000x2gl registers */
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UINT8 level; /* 8259a interrupt level for this device */
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UINT8 ier; /* copy of ier */
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UINT8 lcr; /* copy of lcr, not used by rm9000x2gl driver */
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UINT8 mcr; /* copy of modem control register */
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UINT8 pad1;
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UINT16 channelMode; /* such as INT, POLL modes */
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UINT16 regDelta; /* register address spacing */
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int baudRate;
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UINT32 xtal; /* UART clock frequency */
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UINT32 options; /* hardware setup options */
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} RM9000x2gl_CHAN;
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/* function declarations */
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#if defined(__STDC__) || defined(__cplusplus)
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extern void rm9000x2glInt (RM9000x2gl_CHAN *);
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extern void rm9000x2glDevInit (RM9000x2gl_CHAN *);
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#else
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extern void rm9000x2glInt ();
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extern void rm9000x2glDevInit ();
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#endif /* __STDC__ */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCrm9000x2glSioh */
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