151 lines
5.9 KiB
C
151 lines
5.9 KiB
C
/* taskMipsLib.h - generic kernel interface header */
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/*
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* Copyright (c) 1991-1993, 2001, 2003, 2007, 2009-2011
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* Wind River Systems, Inc.
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*
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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* This file has been developed or significantly modified by the
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* MIPS Center of Excellence Dedicated Engineering Staff.
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* This notice is as per the MIPS Center of Excellence Master Partner
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* Agreement, do not remove this notice without checking first with
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* WR/Platforms MIPS Center of Excellence engineering management.
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*/
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/*
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modification history
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--------------------
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01r,31may11,slk Add extended interrupts for RMI _xlp variant
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01q,27may10,d_c Rename CAVIUM_CNMIPS_* to _WRS_CAVIUM_CNMIPS_* and define in
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arch Makefile
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01p,31mar10,d_c Add cav_cn5xxx and cav_cn6xxx variants
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01o,01may09,slk add flag to TCB to identify task context saved TCB
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01n,26sep07,d_c Add extended interrupts for RMI _xlr variant
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01m,10aug07,rlg MIPS library restructure changes
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01l,29jul07,pes Addition of more registers for Cavium save/restore
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01k,11sep03,jmt Modify Exception Stack for Base 6
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01j,22aug03,jmt Add MMU Support
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01i,16jul01,ros add CofE comment
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01h,18oct93,cd added R4000 support.
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01g,02apr93,caf prototyped taskSRInit().
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01f,22sep92,rrr added support for c++
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01e,03jun92,ajm updated file name references to match real name
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01d,26may92,rrr the tree shuffle
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01c,04oct91,rrr passed through the ansification filter
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-fixed #else and #endif
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-changed copyright notice
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01b,28may91,ajm reordered WIND_TCB_REGS order due to REG_SET change
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01a,01may91,ajm split/derived from 68k version 01k.
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*/
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#ifndef __INCtaskMipsLibh
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#define __INCtaskMipsLibh
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#include <arch/mips/archMips.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define WIND_TCB_GREG_BASE (WIND_TCB_REGS+2*4+2*_RTypeSize)
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#define WIND_TCB_GREG_OFFSET(n) (WIND_TCB_GREG_BASE + (n)*_RTypeSize)
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#define WIND_TCB_SR (WIND_TCB_REGS + 0*4)
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#define WIND_TCB_PC (WIND_TCB_REGS + 1*4)
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#define WIND_TCB_LO (WIND_TCB_REGS + 2*4+0*_RTypeSize)
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#define WIND_TCB_HI (WIND_TCB_REGS + 2*4+1*_RTypeSize)
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#define WIND_TCB_ZERO WIND_TCB_GREG_OFFSET(0)
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#define WIND_TCB_AT WIND_TCB_GREG_OFFSET(1)
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#define WIND_TCB_V0 WIND_TCB_GREG_OFFSET(2)
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#define WIND_TCB_V1 WIND_TCB_GREG_OFFSET(3)
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#define WIND_TCB_A0 WIND_TCB_GREG_OFFSET(4)
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#define WIND_TCB_A1 WIND_TCB_GREG_OFFSET(5)
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#define WIND_TCB_A2 WIND_TCB_GREG_OFFSET(6)
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#define WIND_TCB_A3 WIND_TCB_GREG_OFFSET(7)
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#define WIND_TCB_T0 WIND_TCB_GREG_OFFSET(8)
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#define WIND_TCB_T1 WIND_TCB_GREG_OFFSET(9)
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#define WIND_TCB_T2 WIND_TCB_GREG_OFFSET(10)
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#define WIND_TCB_T3 WIND_TCB_GREG_OFFSET(11)
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#define WIND_TCB_T4 WIND_TCB_GREG_OFFSET(12)
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#define WIND_TCB_T5 WIND_TCB_GREG_OFFSET(13)
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#define WIND_TCB_T6 WIND_TCB_GREG_OFFSET(14)
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#define WIND_TCB_T7 WIND_TCB_GREG_OFFSET(15)
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#define WIND_TCB_S0 WIND_TCB_GREG_OFFSET(16)
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#define WIND_TCB_S1 WIND_TCB_GREG_OFFSET(17)
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#define WIND_TCB_S2 WIND_TCB_GREG_OFFSET(18)
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#define WIND_TCB_S3 WIND_TCB_GREG_OFFSET(19)
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#define WIND_TCB_S4 WIND_TCB_GREG_OFFSET(20)
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#define WIND_TCB_S5 WIND_TCB_GREG_OFFSET(21)
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#define WIND_TCB_S6 WIND_TCB_GREG_OFFSET(22)
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#define WIND_TCB_S7 WIND_TCB_GREG_OFFSET(23)
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#define WIND_TCB_T8 WIND_TCB_GREG_OFFSET(24)
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#define WIND_TCB_T9 WIND_TCB_GREG_OFFSET(25)
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#define WIND_TCB_K0 WIND_TCB_GREG_OFFSET(26)
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#define WIND_TCB_K1 WIND_TCB_GREG_OFFSET(27)
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#define WIND_TCB_GP WIND_TCB_GREG_OFFSET(28)
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#define WIND_TCB_SP WIND_TCB_GREG_OFFSET(29)
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#define WIND_TCB_S8 WIND_TCB_GREG_OFFSET(30)
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#define WIND_TCB_RA WIND_TCB_GREG_OFFSET(31)
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#define WIND_TCB_GREG_END (WIND_TCB_GREG_BASE+32*_RTypeSize)
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#define WIND_TCB_WDB_CAUSE (WIND_TCB_GREG_END + 0*4)
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#define WIND_TCB_WDB_FPCSR (WIND_TCB_GREG_END + 1*4)
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#define WIND_TCB_INTCTRL (WIND_TCB_GREG_END + 2*4)
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#define WIND_TCB_EXTRA1 (WIND_TCB_GREG_END + 3*4)
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#define WIND_TCB_TLBHI (WIND_TCB_GREG_END + 4*4 + 0*_RTypeSize)
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#define WIND_TCB_EXTRA2 (WIND_TCB_GREG_END + 4*4 + 1*_RTypeSize)
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#define WIND_TCB_EXTRA3 (WIND_TCB_GREG_END + 4*4 + 2*_RTypeSize)
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#define WIND_TCB_EXTRA4 (WIND_TCB_GREG_END + 4*4 + 3*_RTypeSize)
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#define WIND_TCB_EXTRA5 (WIND_TCB_GREG_END + 4*4 + 4*_RTypeSize)
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#define WIND_TCB_EXTRA6 (WIND_TCB_GREG_END + 4*4 + 5*_RTypeSize)
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#define WIND_TCB_EXTRA7 (WIND_TCB_GREG_END + 4*4 + 6*_RTypeSize)
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#define WIND_TCB_EXTRA8 (WIND_TCB_GREG_END + 4*4 + 7*_RTypeSize)
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#define WIND_TCB_EXTRA9 (WIND_TCB_GREG_END + 4*4 + 8*_RTypeSize)
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#define WIND_TCB_EXTRA10 (WIND_TCB_GREG_END + 4*4 + 9*_RTypeSize)
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/* flag to identify TCB context was saved from task mode */
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#define WIND_TCB_TASK_CONTEXT WIND_TCB_EXTRA1
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#if defined(_WRS_CAVIUM_CNMIPS_CORE) || defined(_WRS_CAVIUM_CNMIPS_II_CORE)
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#define WIND_TCB_P0 WIND_TCB_EXTRA3
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#define WIND_TCB_P1 WIND_TCB_EXTRA4
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#define WIND_TCB_P2 WIND_TCB_EXTRA5
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#define WIND_TCB_MPL0 WIND_TCB_EXTRA6
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#define WIND_TCB_MPL1 WIND_TCB_EXTRA7
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#define WIND_TCB_MPL2 WIND_TCB_EXTRA8
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#define WIND_TCB_TLO WIND_TCB_EXTRA9
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#define WIND_TCB_THI WIND_TCB_EXTRA10
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#endif /* defined(_WRS_CAVIUM_CNMIPS_CORE) || defined(_WRS_CAVIUM_CNMIPS_II_CORE) */
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#if defined(MIPSXX_xlr) || defined(MIPSXX_xlp)
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#define WIND_TCB_EIMR WIND_TCB_EXTRA3
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#endif /* defined(MIPSXX_xlr) || defined(MIPSXX_xlp) */
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#ifndef _ASMLANGUAGE
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#if defined(__STDC__) || defined(__cplusplus)
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extern ULONG taskSRInit (ULONG newValue);
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#if defined(MIPSXX_xlr) || defined(MIPSXX_xlp)
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extern UINT64 taskExtendedIntInit (UINT64 newValue);
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#endif /* defined(MIPSXX_xlr) || defined(MIPSXX_xlp) */
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#else /* __STDC__ */
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extern ULONG taskSRInit ();
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#if defined(MIPSXX_xlr) || defined(MIPSXX_xlp)
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extern UINT64 taskExtendedIntInit ();
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#endif /* defined(MIPSXX_xlr) || defined(MIPSXX_xlp) */
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#endif /* __STDC__ */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCtaskMipsLibh */
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