769 lines
29 KiB
C
769 lines
29 KiB
C
/* motTsecEnd.h - Motorola TSEC Ethernet network interface.*/
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/*
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* Copyright (c) 2003-2009 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01r,05feb09,wap Complete driver rewrite (legacy maintenance)
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01q,22mar07,dlk Remove references to netJobInfo.
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01p,06mar06,dlk Initialize the RXIC register.
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01o,26jun05,dlk Replace netJobAdd() with jobQueuePost().
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01j,24mar05,dtr Changes from code review.
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01i,31jan05,dtr Decouple from interrupt controller.
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01h,23nov04,rcs Fixed SPR 104568 - fails large pings when attached to a
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gigabit switch
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01g,22oct04,dtr Added Interrupt coalescing defines. Changed some defaults
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for increased performance.SPR 102536
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01f,22jul04,rcs Added PHY Access definitions
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01e,21jun04,mil Changed cacheArchXXX funcs to cacheXXX funcs.
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01d,27apr04,mdo Latest updates for B6 build
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01c,13apr04,mil Fixed location of header file.
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01c,26mar04,rcs Fixed SPR 95432
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01b,12feb04,rcs Adjusted default settings
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01b,04feb04,mil Fixed problem if compiled with GNU.
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01a,10mar03,gjc Motorola TSEC Ethernet.
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*/
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#ifndef __INCmotTsecEndh
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#define __INCmotTsecEndh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef BSP_VERSION
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#define TSEC_IEVENT 0x010
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#define TSEC_IMASK 0x014
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#define TSEC_EDIS 0x018
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#define TSEC_ECNTRL 0x020
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#define TSEC_MINFLR 0x024
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#define TSEC_PTV 0x028
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#define TSEC_DMACTRL 0x02C
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#define TSEC_TBIPA 0x030
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#define TSEC_FIFO_PAUSE_CTRL 0x04C
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#define TSEC_FIFO_TX_THR 0x08C
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#define TSEC_FIFO_STRV 0x098
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#define TSEC_FIFO_STRV_SHUT 0x09C
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#define TSEC_TCTRL 0x100
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#define TSEC_TSTAT 0x104
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#define TSEC_TBDLEN 0x10C
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#define TSEC_TXIC 0x110
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#define TSEC_CTBPTR 0x124
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#define TSEC_TBPTR 0x184
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#define TSEC_TBASE 0x204
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#define TSEC_OSTBD 0x2b0
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#define TSEC_OSTBDP 0x2b4
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#define TSEC_RCTRL 0x300
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#define TSEC_RSTAT 0x304
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#define TSEC_RBDLEN 0x30C
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#define TSEC_RXIC 0x310
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#define TSEC_CRBPTR 0x324
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#define TSEC_MRBLR 0x340
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#define TSEC_RBPTR 0x384
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#define TSEC_RBASE 0x404
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#define TSEC_MACCFG1 0x500
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#define TSEC_MACCFG2 0x504
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#define TSEC_IPGIFG 0x508
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#define TSEC_HAFDUP 0x50C
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#define TSEC_MAXFRM 0x510
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#define TSEC_MIIMCFG 0x520
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#define TSEC_MIIMCOM 0x524
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#define TSEC_MIIMADD 0x528
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#define TSEC_MIIMCON 0x52C
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#define TSEC_MIIMSTAT 0x530
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#define TSEC_MIIMIND 0x534
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#define TSEC_IFSTAT 0x53C
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#define TSEC_PAR0 0x540
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#define TSEC_PAR1 0x544
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#define TSEC_TR64 0x680
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#define TSEC_TR127 0x684
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#define TSEC_TR255 0x688
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#define TSEC_TR511 0x68C
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#define TSEC_TR1K 0x690
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#define TSEC_TRMAX 0x694
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#define TSEC_TRMGV 0x698
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#define TSEC_RBYT 0x69C
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#define TSEC_RPKT 0x6A0
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#define TSEC_RFCS 0x6A4
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#define TSEC_RMCA 0x6A8
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#define TSEC_RBCA 0x6AC
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#define TSEC_RXCF 0x6B0
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#define TSEC_RXPF 0x6B4
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#define TSEC_RXUO 0x6B8
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#define TSEC_RALN 0x6BC
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#define TSEC_RFLR 0x6C0
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#define TSEC_RCDE 0x6C4
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#define TSEC_RCSE 0x6C8
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#define TSEC_RUND 0x6CC
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#define TSEC_ROVR 0x6D0
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#define TSEC_RFRG 0x6D4
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#define TSEC_RJBR 0x6D8
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#define TSEC_RDRP 0x6DC
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#define TSEC_TBYT 0x6E0
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#define TSEC_TPKT 0x6E4
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#define TSEC_TMCA 0x6E8
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#define TSEC_TBCA 0x6EC
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#define TSEC_TXPF 0x6F0
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#define TSEC_TDFR 0x6F4
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#define TSEC_TEDF 0x6F8
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#define TSEC_TSCL 0x6FC
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#define TSEC_TMCL 0x700
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#define TSEC_TLCL 0x704
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#define TSEC_TXCL 0x708
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#define TSEC_TNCL 0x70C
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#define TSEC_TDRP 0x714
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#define TSEC_TJBR 0x718
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#define TSEC_TFCS 0x71C
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#define TSEC_TXCF 0x720
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#define TSEC_TOVR 0x724
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#define TSEC_TUND 0x728
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#define TSEC_TFRG 0x72C
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#define TSEC_CAR1 0x730
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#define TSEC_CAR2 0x734
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#define TSEC_CAM1 0x738
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#define TSEC_CAM2 0x73C
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#define TSEC_IADDR0 0x800
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#define TSEC_IADDR1 0x804
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#define TSEC_IADDR2 0x808
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#define TSEC_IADDR3 0x80C
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#define TSEC_IADDR4 0x810
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#define TSEC_IADDR5 0x814
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#define TSEC_IADDR6 0x818
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#define TSEC_IADDR7 0x81C
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#define TSEC_GADDR0 0x880
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#define TSEC_GADDR1 0x884
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#define TSEC_GADDR2 0x888
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#define TSEC_GADDR3 0x88C
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#define TSEC_GADDR4 0x890
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#define TSEC_GADDR5 0x894
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#define TSEC_GADDR6 0x898
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#define TSEC_GADDR7 0x89C
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#define TSEC_ATTR 0xBF8
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#define TSEC_ATTRELI 0xBFC
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/* IEVENT and IMASK Register definitions */
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#define TSEC_IEVENT_BABR 0x80000000 /* giant frame RXed */
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#define TSEC_IEVENT_RXC 0x40000000 /* pause frame RXed */
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#define TSEC_IEVENT_BSY 0x20000000 /* RX overrun */
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#define TSEC_IEVENT_EBERR 0x10000000 /* eth bus error */
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#define TSEC_IEVENT_MSRO 0x04000000 /* stats oflow */
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#define TSEC_IEVENT_GTSC 0x02000000 /* graceful TX stop done */
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#define TSEC_IEVENT_BABT 0x01000000 /* giant frame TXed */
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#define TSEC_IEVENT_TXC 0x00800000 /* pause frame TXed */
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#define TSEC_IEVENT_TXE 0x00400000 /* TX error */
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#define TSEC_IEVENT_TXB 0x00200000 /* TX descriptor updated */
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#define TSEC_IEVENT_TXF 0x00100000 /* TX frame completed */
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#define TSEC_IEVENT_LC 0x00040000 /* late collision */
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#define TSEC_IEVENT_CRL 0x00020000 /* excess collision */
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#define TSEC_IEVENT_XFUN 0x00010000 /* TX underrun */
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#define TSEC_IEVENT_RXB 0x00008000 /* RX descriptor updated */
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#define TSEC_IEVENT_MMRD 0x00000400 /* MDIO read, 8349 only */
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#define TSEC_IEVENT_MMWR 0x00000200 /* MDIO write, 8349 only */
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#define TSEC_IEVENT_GRSC 0x00000100 /* graceful RX stop done */
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#define TSEC_IEVENT_RXF 0x00000080 /* RX frame completed */
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/*
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* Error event disable register. Note that with the IMASK
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* register, setting a bit enables the interrupt, whereas with
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* this register, setting a bit disables the interrupt.
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*/
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#define TSEC_EDIS_BSYDIS 0x20000000
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#define TSEC_EDIS_EBERRDIS 0x10000000
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#define TSEC_EDIS_TXEDIS 0x00400000
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#define TSEC_EDIS_LCDIS 0x00040000
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#define TSEC_EDIS_CRLDIS 0x00020000
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#define TSEC_EDIS_XFUNDIS 0x00010000
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/* Ethernet Control Register */
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#define TSEC_ECNTRL_CLRCNT 0x00004000 /* zero status counters */
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#define TSEC_ECNTRL_AUTOZ 0x00002000 /* zero counter on read */
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#define TSEC_ECNTRL_STEN 0x00001000 /* status enable */
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#define TSEC_ECNTRL_GMIIM 0x00000040 /* GMII mode (strap) */
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#define TSEC_ECNTRL_TBIM 0x00000020 /* TBI mode (strap) */
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#define TSEC_ECNTRL_RPM 0x00000010 /* reduced pin mode 1000 */
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#define TSEC_ECNTRL_R100M 0x00000008 /* 0 = R10, 1 == R100 */
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#define TSEC_ECNTRL_RMM 0x00000004 /* reduced pin mode 10/100*/
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/* Pause time value register */
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#define TSEC_PTV_PT 0x0000FFFF /* pause time value */
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#define TSEC_PTV_PTE 0xFFFF0000 /* extended pause control */
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/* DMA control register */
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#define TSEC_DMACTRL_TDSEN 0x00000080 /* TX data snoop */
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#define TSEC_DMACTRL_TBDSEN 0x00000040 /* TX bd snoop */
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#define TSEC_DMACTRL_GRS 0x00000010 /* graceful RX stop */
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#define TSEC_DMACTRL_GTS 0x00000008 /* graceful TX stop */
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#define TSEC_DMACTRL_TOD 0x00000004 /* TX on demand */
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#define TSEC_DMACTRL_WWR 0x00000002 /* write with response */
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#define TSEC_DMACTRL_WOP 0x00000001 /* wait or poll */
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/* Transmit control register */
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#define TSEC_TCTRL_THDF 0x00000800 /* half duplex flow ctl */
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#define TSEC_TCTRL_RFC_PAUSE 0x00000010 /* received pause frame */
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#define TSEC_TCTRL_TFC_PAUSE 0x00000008 /* send pause frame */
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/*
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* Transmit status register
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* The THLT bit will be set whenever the TX DMA engine encounters
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* an error condition, including when it runs out of ready descriptors
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* to process. The transmitter is resumed by clearing the bit (i.e.
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* writing 0 to this register).
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*/
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#define TSEC_TSTAT_THLT 0x80000000 /* TX halted / resume */
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/* Transmit interrupt coalescing register */
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#define TSEC_TXIC_ICEN 0x80000000 /* TX coal enable */
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#define TSEC_TXIC_ICFCT 0x1FE00000 /* frame count thresh */
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#define TSEC_TXIC_ICTT 0x0000FFFF /* timer thresh */
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/* Receive control register */
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#define TSEC_RCTRL_BC_REJ 0x00000010 /* reject broadcasts */
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#define TSEC_RCTRL_PROM 0x00000008 /* promisc mode */
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#define TSEC_RCTRL_RSF 0x00000004 /* receive short frames */
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/*
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* Receive status register
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* Like the TSTAT register, the QHLT bit indicates the RX DMA engine
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* has stalled due to running out of descriptors, or encountering an
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* error. The bit must be cleared to resume the RX engine.
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*/
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#define TSEC_RSTAT_QHLT 0x00800000 /* RX halted / resume */
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/* Receive interrupt coalescing register */
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#define TSEC_RXIC_ICEN 0x80000000 /* RX coal enable */
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#define TSEC_RXIC_ICFCT 0x1FE00000 /* frame count thresh */
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#define TSEC_RXIC_ICTT 0x0000FFFF /* timer thresh */
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#define TSEC_COAL_FRAMES(x) ((x) & 0xFF) << 21
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#define TSEC_COAL_TIMER(x) ((x) & 0xFFFF)
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/* MAC configuration 1 register */
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#define TSEC_MACCFG1_SOFT_RESET 0x80000000 /* Reset the entire MAC */
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#define TSEC_MACCFG1_RESET_RX_MC 0x00080000 /* Reset RX mac control */
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#define TSEC_MACCFG1_RESET_TX_MC 0x00040000 /* Reset TX mac control */
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#define TSEC_MACCFG1_RESET_RX_FUN 0x00020000 /* Reset RX function */
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#define TSEC_MACCFG1_RESET_TX_FUN 0x00010000 /* Reset TX function */
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#define TSEC_MACCFG1_LOOPBACK 0x00000100 /* MAC loopback mode */
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#define TSEC_MACCFG1_RX_FLOW 0x00000020 /* enable RX flow control */
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#define TSEC_MACCFG1_TX_FLOW 0x00000010 /* enable TX flow control */
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#define TSEC_MACCFG1_SYNCD_RX_EN 0x00000008 /* RX sync'ed */
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#define TSEC_MACCFG1_RX_EN 0x00000004 /* RX enable */
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#define TSEC_MACCFG1_SYNCD_TX_EN 0x00000002 /* TX sync'ed */
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#define TSEC_MACCFG1_TX_EN 0x00000001 /* TX enable */
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/* MAC configuration 2 register */
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#define TSEC_MACCFG2_IF_MODE_MASK 0x00000003
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#define TSEC_MACCFG2_IF_MODE_MII 0x00000001
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#define TSEC_MACCFG2_IF_MODE_GMII_TBI 0x00000002
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#define TSEC_MACCFG2_PREAMBLE_LEN 0x0000F000
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#define TSEC_MACCFG2_IF_MODE 0x00000300
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#define TSEC_MACCFG2_HUGE_FRAME 0x00000020
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#define TSEC_MACCFG2_LENGTH_CHECK 0x00000010
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#define TSEC_MACCFG2_PADCRC 0x00000004
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#define TSEC_MACCFG2_CRC_EN 0x00000002
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#define TSEC_MACCFG2_FULL_DUPLEX 0x00000001
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#define TSEC_IFMODE_RSVD0 0x00000000
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#define TSEC_IFMODE_MII 0x00000100 /* nibble mode */
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#define TSEC_IFMODE_GMII_TBI 0x00000200 /* byte mode */
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#define TSEC_IFMODE_RSVD1 0x00000300
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/* Interpacket gap register */
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#define TSEC_IPGIFG_BACKTOBACK 0x0000007F
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#define TSEC_IPGIFG_MINIMUM 0x00007F00
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#define TSEC_IPGIFG_NONBACKTOBACK1 0x007F0000
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#define TSEC_IPGIFG_NONBACKTOBACK2 0x7F000000
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/* Halfduplex register */
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#define TSEC_HALFDUP_ALTBEB_TRUNC 0x00F00000
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#define TSEC_HALFDUP_BEB 0x00080000
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#define TSEC_HALFDUP_BPNBO 0x00040000
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#define TSEC_HALFDUP_NBO 0x00020000
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#define TSEC_HALFDUP_EXCESS_DEF 0x00010000
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#define TSEC_HALFDUP_RETRY 0x0000F000
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#define TSEC_HALFDUP_COL_WINDOW 0x0000003F
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/* MII management configuration register */
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#define TSEC_MIIMCFG_RESET 0x80000000
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#define TSEC_MIIMCFG_NO_PRE 0x00000010
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#define TSEC_MIIMCFG_MGMT_CLK 0x0000000F
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#define TSEC_MIIMCFG_MCS_2 0x00000000
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#define TSEC_MIIMCFG_MCS_4 0x00000001
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#define TSEC_MIIMCFG_MCS_6 0x00000002
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#define TSEC_MIIMCFG_MCS_8 0x00000003
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#define TSEC_MIIMCFG_MCS_10 0x00000004
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#define TSEC_MIIMCFG_MCS_14 0x00000005
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#define TSEC_MIIMCFG_MCS_20 0x00000006
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#define TSEC_MIIMCFG_MCS_28 0x00000007
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/* MII management command register */
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#define TSEC_MIIMCOM_SCAN 0x00000002
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#define TSEC_MIIMCOM_READ 0x00000001
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/* MII management address register */
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#define TSEC_MIIMADD_PHYADDR 0x0000001F
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#define TSEC_MIIMADD_REGADDR 0x00001F00
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/* MII management control register */
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#define TSEC_MIIMCON_WRDATA 0x0000FFFF
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/* MII management status register */
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#define TSEC_MIIMSTAT_RDDATA 0x0000FFFF
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/* MII management indicator register */
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#define TSEC_MIIMIND_NOT_VALID 0x00000004
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#define TSEC_MIIMIND_SCAN 0x00000002
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#define TSEC_MIIMIND_BUSY 0x00000001
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/* Attribute register */
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#define TSEC_ATTR_ELCWT 0x00006000 /* data L2 cache extract */
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#define TSEC_ATTR_BDLWT 0x00000C00 /* BD L2 cache extract */
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#define TSEC_ATTR_RDSEN 0x00000080 /* RX buffer snooping */
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#define TSEC_ATTR_RBDSEN 0x00000040 /* RX descriptor snooping */
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#define TSEC_ELCWT_NONE 0x00000000
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#define TSEC_ELCWT_RSVD 0x00002000
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#define TSEC_ELCWT_L2 0x00004000
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#define TSEC_ELCWT_L2_LOCK 0x00006000
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#define TSEC_BDLWT_NONE 0x00000000
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#define TSEC_BDLWT_RSVD 0x00000400
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#define TSEC_BDLWT_L2 0x00000800
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#define TSEC_BDLWT_L2_LOCK 0x00000C00
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/* Attribute extract length and index register */
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#define TSEC_ATTRELI_EXTLEN 0x3FFF0000
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#define TSEC_ATTRELI_EXTIDX 0x00003FFF
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#define TSEC_ATTRELI_EL(x) (((x) & 0x3FFF) << 16)
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#define TSEC_ATTRELI_EI(x) ((x) & 0x3FFF)
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/*
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* Buffer descriptor format
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*
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* The descriptor structure is always 8 bytes. For the ETSEC, there's
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* an additional field frame descriptor field which is hidden in
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* the packet buffer, which is used for specifying additional
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* information related to checksum offload.
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*
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* The descriptor layout is much the same as it is for all of
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* Motorola/Freescale's ethernet MACs (including the TSEC, SCC
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* and CPM). There's a 16 bit status field, 16 bit length field,
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* and a 32-bit address field. Each descriptor describes a single
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* fragment. The last fragment has the 'last in frame' bit set.
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* Since there is no 'next' pointer, descriptors are allocated
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* in contiguous arrays. The last descriptor in the array must
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* have the 'wrap' bit set.
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*/
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typedef struct tsecDesc
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{
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volatile UINT16 bdSts;
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volatile UINT16 bdLen;
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volatile UINT32 bdAddr;
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} TSEC_DESC;
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/* Transmit descriptor status bits */
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#define TSEC_TBD_R 0x8000 /* owner, 0 == host, 1 == chip */
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#define TSEC_TBD_PADCRC 0x4000 /* autopad and append CRC */
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#define TSEC_TBD_W 0x2000 /* wrap, last descriptor in ring */
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#define TSEC_TBD_I 0x1000 /* interrupt after processing is done */
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#define TSEC_TBD_L 0x0800 /* last descriptor in frame */
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#define TSEC_TBD_TC 0x0400 /* append CRC */
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#define TSEC_TBD_DEF 0x0200 /* excess deferral condition */
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#define TSEC_TBD_TO1 0x0100 /* software scratch bit */
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#define TSEC_TBD_HFE_LC 0x0080 /* huge frame, or late collision */
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#define TSEC_TBD_RL 0x0040 /* retry limit exceeded */
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#define TSEC_TBD_RC 0x003C /* retry count */
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#define TSEC_TBD_UN 0x0002 /* TX underrun */
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#define TSEC_TBD_TR 0x0001 /* packet truncated */
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/* Receive descriptor status bits */
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#define TSEC_RBD_E 0x8000 /* owner, 0 == host, 1 == chip */
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#define TSEC_RBD_RO1 0x4000 /* software scratch bit */
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#define TSEC_RBD_W 0x2000 /* wrap, last descriptor in ring */
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#define TSEC_RBD_I 0x1000 /* interrupt after processing is done */
|
|
#define TSEC_RBD_L 0x0800 /* last descriptor in frame */
|
|
#define TSEC_RBD_F 0x0400 /* first descriptor in frame */
|
|
#define TSEC_RBD_M 0x0200 /* filter miss */
|
|
#define TSEC_RBD_BC 0x0080 /* broadcast frame */
|
|
#define TSEC_RBD_MC 0x0040 /* multicast frame */
|
|
#define TSEC_RBD_LG 0x0020 /* giant frame error */
|
|
#define TSEC_RBD_NO 0x0010 /* alignment error */
|
|
#define TSEC_RBD_SH 0x0008 /* runt frame error */
|
|
#define TSEC_RBD_CR 0x0004 /* CRC error */
|
|
#define TSEC_RBD_OV 0x0002 /* FIFO overrun */
|
|
#define TSEC_RBD_TR 0x0001 /* packet truncated */
|
|
|
|
#define TSEC_RX_DESC_CNT 128
|
|
#define TSEC_TX_DESC_CNT 128
|
|
|
|
/*#define TSEC_INC_DESC(x, y) (x) = (((x) + 1) % y)*/
|
|
#define TSEC_INC_DESC(x, y) (x) = ((x + 1) & (y - 1))
|
|
#define TSEC_MAXFRAG 16
|
|
#define TSEC_MAX_RX 16
|
|
|
|
#define TSEC_MTU 1500
|
|
#define TSEC_JUMBO_MTU 9000
|
|
#define TSEC_CLSIZE 1600
|
|
#define TSEC_JUMBO_CLSIZE 9056
|
|
|
|
#define TSEC_BOUND (_CACHE_ALIGN_SIZE - 1)
|
|
#define TSEC_ALIGN(x) \
|
|
(char *)(((UINT32)(x) + (TSEC_BOUND)) & ~(TSEC_BOUND))
|
|
|
|
#define TSEC_ADJ(x) \
|
|
(x)->m_data = TSEC_ALIGN((x)->m_data)
|
|
|
|
#define TSEC_NAME "mottsec"
|
|
#define TSEC_TIMEOUT 10000
|
|
#define TSEC_INTRS (TSEC_RXINTRS|TSEC_TXINTRS|TSEC_ERRINTRS)
|
|
#define TSEC_RXINTRS (/*TSEC_IEVENT_RXB|*/TSEC_IEVENT_RXF|TSEC_IEVENT_RXC)
|
|
#define TSEC_TXINTRS (/*TSEC_IEVENT_TXB|*/TSEC_IEVENT_TXF|TSEC_IEVENT_TXC)
|
|
#define TSEC_ERRINTRS (TSEC_IEVENT_XFUN|TSEC_IEVENT_EBERR|TSEC_IEVENT_BSY)
|
|
|
|
#define ETHER_CRC_LEN 4
|
|
#define ETHER_CRC_POLY_BE 0x04c11db6
|
|
|
|
#ifndef MII_SR_EXT_STS
|
|
#define MII_SR_EXT_STS 0x0100 /* extended sts in reg 15 */
|
|
#endif
|
|
|
|
#ifndef MII_CR_1000
|
|
#define MII_CR_1000 0x0040 /* 1 = 1000mb when
|
|
MII_CR_100 is also 1 */
|
|
#endif
|
|
|
|
#define bswap16(x) ((LSB(x) << 8) | MSB(x))
|
|
#define bswap32(x) LONGSWAP((UINT32)(x))
|
|
#define bswap64(x) /* not yet */
|
|
|
|
typedef struct endNetPool
|
|
{
|
|
NET_POOL pool;
|
|
void * pMblkMemArea;
|
|
void * pClMemArea;
|
|
} END_NET_POOL;
|
|
|
|
#define tsecEndPoolTupleFree(x) netMblkClChainFree(x)
|
|
#define tsecEndPoolTupleGet(x) \
|
|
netTupleGet((x), (x)->clTbl[0]->clSize, M_DONTWAIT, MT_DATA, 0)
|
|
|
|
#define IFM_ETHER 0x00000020
|
|
#define IFM_10_T 3 /* 10BaseT - RJ45 */
|
|
#define IFM_10_2 4 /* 10Base2 - Thinnet */
|
|
#define IFM_10_5 5 /* 10Base5 - AUI */
|
|
#define IFM_100_TX 6 /* 100BaseTX - RJ45 */
|
|
#define IFM_100_FX 7 /* 100BaseFX - Fiber */
|
|
#define IFM_100_T4 8 /* 100BaseT4 - 4 pair cat 3 */
|
|
#define IFM_100_VG 9 /* 100VG-AnyLAN */
|
|
#define IFM_100_T2 10 /* 100BaseT2 */
|
|
#define IFM_1000_SX 11 /* 1000BaseSX - multi-mode fiber */
|
|
#define IFM_10_STP 12 /* 10BaseT over shielded TP */
|
|
#define IFM_10_FL 13 /* 10BaseFL - Fiber */
|
|
#define IFM_1000_LX 14 /* 1000baseLX - single-mode fiber */
|
|
#define IFM_1000_CX 15 /* 1000baseCX - 150ohm STP */
|
|
#define IFM_1000_T 16 /* 1000baseT - 4 pair cat 5 */
|
|
#define IFM_HPNA_1 17 /* HomePNA 1.0 (1Mb/s) */
|
|
|
|
/*
|
|
* Shared media sub-types
|
|
*/
|
|
#define IFM_AUTO 0 /* Autoselect best media */
|
|
#define IFM_MANUAL 1 /* Jumper/dipswitch selects media */
|
|
#define IFM_NONE 2 /* Deselect all media */
|
|
|
|
/*
|
|
* Shared options
|
|
*/
|
|
#define IFM_FDX 0x00100000 /* Force full duplex */
|
|
#define IFM_HDX 0x00200000 /* Force half duplex */
|
|
#define IFM_FLAG0 0x01000000 /* Driver defined flag */
|
|
#define IFM_FLAG1 0x02000000 /* Driver defined flag */
|
|
#define IFM_FLAG2 0x04000000 /* Driver defined flag */
|
|
#define IFM_LOOP 0x08000000 /* Put hardware in loopback */
|
|
|
|
/*
|
|
* Masks
|
|
*/
|
|
#define IFM_NMASK 0x000000e0 /* Network type */
|
|
#define IFM_TMASK 0x0000001f /* Media sub-type */
|
|
#define IFM_IMASK 0xf0000000 /* Instance */
|
|
#define IFM_ISHIFT 28 /* Instance shift */
|
|
#define IFM_OMASK 0x0000ff00 /* Type specific options */
|
|
#define IFM_MMASK 0x00070000 /* Mode */
|
|
#define IFM_MSHIFT 16 /* Mode shift */
|
|
#define IFM_GMASK 0x0ff00000 /* Global options */
|
|
|
|
/*
|
|
* Status bits
|
|
*/
|
|
#define IFM_AVALID 0x00000001 /* Active bit valid */
|
|
#define IFM_ACTIVE 0x00000002 /* Interface attached to working net */
|
|
|
|
/*
|
|
* Macros to extract various bits of information from the media word.
|
|
*/
|
|
#define IFM_TYPE(x) ((x) & IFM_NMASK)
|
|
#define IFM_SUBTYPE(x) ((x) & IFM_TMASK)
|
|
#define IFM_TYPE_OPTIONS(x) ((x) & IFM_OMASK)
|
|
#define IFM_INST(x) (((x) & IFM_IMASK) >> IFM_ISHIFT)
|
|
#define IFM_OPTIONS(x) ((x) & (IFM_OMASK|IFM_GMASK))
|
|
#define IFM_MODE(x) ((x) & IFM_MMASK)
|
|
|
|
#define IFM_INST_MAX IFM_INST(IFM_IMASK)
|
|
|
|
typedef struct _TSEC_END_MEDIA
|
|
{
|
|
UINT32 endMediaActive;
|
|
UINT32 endMediaStatus;
|
|
} TSEC_END_MEDIA;
|
|
|
|
/* number of seconds to wait between link state checks */
|
|
|
|
#define TSEC_LINKPOLL 2
|
|
|
|
/* Default interrupt vectors */
|
|
|
|
#define TSEC_TXINUM 25
|
|
#define TSEC_RXINUM 26
|
|
#define TSEC_ERRINUM 30
|
|
|
|
#define ETHER_ADDR_LEN 6
|
|
|
|
/*
|
|
* Private adapter context structure.
|
|
*/
|
|
|
|
typedef struct tsec_drv_ctrl
|
|
{
|
|
END_OBJ tsecEndObj;
|
|
int tsecUnit;
|
|
void * tsecRegBase;
|
|
UINT32 tsecInumTx;
|
|
UINT32 tsecInumRx;
|
|
UINT32 tsecInumErr;
|
|
|
|
volatile BOOL tsecErrPending;
|
|
|
|
volatile BOOL tsecRxPending;
|
|
|
|
volatile BOOL tsecTxPending;
|
|
UINT8 tsecTxCur;
|
|
UINT8 tsecTxLast;
|
|
volatile BOOL tsecTxStall;
|
|
UINT16 tsecTxThresh;
|
|
|
|
BOOL tsecPolling;
|
|
M_BLK_ID tsecPollBuf;
|
|
UINT32 tsecIntMask;
|
|
UINT32 tsecRxIntrs;
|
|
UINT32 tsecTxIntrs;
|
|
UINT32 tsecErrIntrs;
|
|
|
|
UINT8 tsecAddr[ETHER_ADDR_LEN];
|
|
|
|
UINT16 tsecMiiSts;
|
|
WDOG_ID tsecMiiWd;
|
|
END_ERR tsecLastError;
|
|
UINT32 tsecCurMedia;
|
|
UINT32 tsecCurStatus;
|
|
struct tsec_drv_ctrl *tsecMiiDev;
|
|
int tsecMiiPhyAddr;
|
|
|
|
/* DMA tags and maps. */
|
|
|
|
TSEC_DESC *tsecRxDesc;
|
|
TSEC_DESC *tsecTxDesc;
|
|
|
|
M_BLK_ID tsecRxMblk[TSEC_RX_DESC_CNT];
|
|
M_BLK_ID tsecTxMblk[TSEC_TX_DESC_CNT];
|
|
|
|
UINT32 tsecTxProd;
|
|
UINT32 tsecTxCons;
|
|
UINT32 tsecTxFree;
|
|
UINT32 tsecRxIdx;
|
|
|
|
SEM_ID tsecDevSem;
|
|
|
|
UINT32 tsecErrInt;
|
|
} TSEC_DRV_CTRL;
|
|
|
|
#define CSR_READ_4(pDev, addr) \
|
|
*(volatile UINT32 *)((UINT32)pDev->tsecRegBase + addr)
|
|
|
|
#define CSR_WRITE_4(pDev, addr, data) \
|
|
do { \
|
|
volatile UINT32 *pReg = \
|
|
(UINT32 *)((UINT32)pDev->tsecRegBase + addr); \
|
|
*(pReg) = (UINT32)(data); \
|
|
WRS_ASM("eieio"); \
|
|
} while ((0))
|
|
|
|
#define CSR_SETBIT_4(pDev, offset, val) \
|
|
CSR_WRITE_4(pDev, offset, CSR_READ_4(pDev, offset) | (val))
|
|
|
|
#define CSR_CLRBIT_4(pDev, offset, val) \
|
|
CSR_WRITE_4(pDev, offset, CSR_READ_4(pDev, offset) & ~(val))
|
|
|
|
|
|
#endif /* BSP_VERSION */
|
|
|
|
/* Compatibility cruft with old motTsecEnd driver */
|
|
|
|
/* MII/PHY PHY_DEF_MODE flags to init the phy driver */
|
|
#define MOT_TSEC_USR_MODE_DEFAULT 0
|
|
#define MOT_TSEC_USR_PHY_NO_AN 0x00000001 /* do not auto-negotiate */
|
|
#define MOT_TSEC_USR_PHY_TBL 0x00000002 /* use negotiation table */
|
|
#define MOT_TSEC_USR_PHY_NO_FD 0x00000004 /* do not use full duplex */
|
|
#define MOT_TSEC_USR_PHY_NO_100 0x00000008 /* do not use 100Mbit speed */
|
|
#define MOT_TSEC_USR_PHY_NO_HD 0x00000010 /* do not use half duplex */
|
|
#define MOT_TSEC_USR_PHY_NO_10 0x00000020 /* do not use 10Mbit speed */
|
|
#define MOT_TSEC_USR_PHY_MON 0x00000040 /* use PHY Monitor */
|
|
#define MOT_TSEC_USR_PHY_ISO 0x00000080 /* isolate a PHY */
|
|
|
|
|
|
/* ECNTRL Ethernet Control */
|
|
#define MOT_TSEC_USR_STAT_CLEAR 0x00000100 /* init + runtime clear mstats*/
|
|
#define MOT_TSEC_USR_STAT_AUTOZ 0x00000200 /* init */
|
|
#define MOT_TSEC_USR_STAT_ENABLE 0x00000400 /* init */
|
|
|
|
/* PHY bus configuration selections */
|
|
#define MOT_TSEC_USR_MODE_MASK 0x0003f800
|
|
#define MOT_TSEC_USR_MODE_TBI 0x00000800
|
|
#define MOT_TSEC_USR_MODE_RTBI 0x00001000
|
|
#define MOT_TSEC_USR_MODE_MII 0x00002000
|
|
#define MOT_TSEC_USR_MODE_GMII 0x00004000
|
|
#define MOT_TSEC_USR_MODE_RGMII 0x00008000
|
|
#define MOT_TSEC_USR_MODE_RGMII_10 0x00010000
|
|
#define MOT_TSEC_USR_MODE_RGMII_100 0x00020000
|
|
|
|
typedef struct
|
|
{
|
|
/* function pointers for BSP and Driver call backs */
|
|
FUNCPTR miiPhyInit; /* BSP Phy driver init callback */
|
|
FUNCPTR miiPhyInt; /* BSP call back to process PHY status change interrupt */
|
|
FUNCPTR miiPhyStatusGet; /* Driver call back to get duplex status */
|
|
FUNCPTR miiPhyRead; /* BSP call back to read MII/PHY registers */
|
|
FUNCPTR miiPhyWrite; /* BSP call back to write MII/PHY registers */
|
|
FUNCPTR enetAddrGet; /* Driver call back to get the Ethernet address */
|
|
FUNCPTR enetAddrSet; /* Driver call back to set the Ethernet address */
|
|
FUNCPTR enetEnable; /* Driver call back to enable the ENET interface */
|
|
FUNCPTR enetDisable; /* Driver call back to disable the ENET interface */
|
|
FUNCPTR extWriteL2AllocFunc; /* Driver call back to put tx bd in L2 */
|
|
} MOT_TSEC_FUNC_TABLE;
|
|
|
|
typedef struct
|
|
{
|
|
UINT32 phyAddr; /* phy physical address */
|
|
UINT32 phyDefMode; /* default mode */
|
|
UINT32 phyMaxDelay; /* max delay */
|
|
UINT32 phyDelayParm; /* poll interval if in poll mode */
|
|
MII_AN_ORDER_TBL * phyAnOrderTbl; /* autonegotiation table */
|
|
} MOT_TSEC_PHY_PARAMS;
|
|
|
|
typedef struct
|
|
{
|
|
UINT8 autonegError; /* 0-N/A, 0 - none, 1- error */
|
|
UINT8 duplex; /* 1 - half, 2- full */
|
|
#define MOT_TSEC_PHY_DUPLEX_HALF (1)
|
|
#define MOT_TSEC_PHY_DUPLEX_FULL (2)
|
|
UINT8 speed; /* 0-N/A, 1 - 10, 2- 100, 3 -1G */
|
|
#define MOT_TSEC_PHY_SPEED_10 (1)
|
|
#define MOT_TSEC_PHY_SPEED_100 (2)
|
|
#define MOT_TSEC_PHY_SPEED_1000 (3)
|
|
UINT8 link; /* 0-N/A, 1 - down, 2- up */
|
|
UINT8 symbolError; /* 0-N/A, 1 - none, 2- error */
|
|
UINT8 autoNegComplete; /* 0-N/A, 1 - no, 2- completed */
|
|
UINT8 energyDetect; /* 0-N/A, 1 - no, 2- detected */
|
|
UINT8 falseCarrier; /* 0-N/A, 1 - no, 2- detected */
|
|
UINT8 downShift; /* 0-N/A, 1 - no, 2- detected */
|
|
UINT8 fifoError; /* 0-N/A, 1 - none, 2- error */
|
|
UINT8 xover; /* 0-N/A, 1 - MDI, 2- MDIX */
|
|
UINT8 polarity; /* 0-N/A, 1 - normal, 2- reversed */
|
|
UINT8 jabber; /* 0-N/A, 1 - no, 2- detected */
|
|
UINT8 pageReceived; /* 0-N/A, 1 - no, 2- detected */
|
|
UINT8 cableLength; /* 0-N/A */
|
|
UINT8 txPause; /* 0-N/A, 1 - no, 2- detected */
|
|
UINT8 rxPause; /* 0-N/A, 1 - no, 2- detected */
|
|
UINT8 farEndFault; /* 0-N/A, 1 - no, 2- detected */
|
|
UINT32 rxErrorCntr; /* 0-N/A, number of rx errors */
|
|
UINT32 reserved[4]; /* future use */
|
|
} MOT_TSEC_PHY_STATUS;
|
|
|
|
typedef struct
|
|
{
|
|
UINT8 *memBufPtr; /* Buffer pointer for allocated buffer space */
|
|
UINT32 memBufSize; /* Buffer pool size */
|
|
void *bdBasePtr; /* Descriptor Base Address */
|
|
UINT32 bdSize; /* Descriptor Size */
|
|
UINT32 rbdNum; /* Number of Receive Buffer Descriptors */
|
|
UINT32 tbdNum; /* Number of Transmit Buffer Descriptors */
|
|
UINT32 unit0TxVec;
|
|
UINT32 unit0RxVec;
|
|
UINT32 unit0ErrVec;
|
|
UINT32 unit1TxVec;
|
|
UINT32 unit1RxVec;
|
|
UINT32 unit1ErrVec;
|
|
} MOT_TSEC_PARAMS;
|
|
|
|
typedef struct
|
|
{
|
|
UINT32 inum_tsecTx; /* Transmit Interrupt */
|
|
UINT32 inum_tsecRx; /* Receive Interrupt */
|
|
UINT32 inum_tsecErr; /* Error Interrupt */
|
|
FUNCPTR inumToIvec; /* function to convert INUM to IVEC */
|
|
FUNCPTR ivecToInum; /* function to convert IVEC to INUM */
|
|
} MOT_TSEC_INT_CTRL;
|
|
|
|
#define MOT_TSEC_MAX_DEVS 2
|
|
#define MOT_TSEC_DEV_1 0
|
|
#define MOT_TSEC_DEV_2 1
|
|
#define MOT_TSEC_ADRS_OFFSET_1 0x00024000
|
|
#define MOT_TSEC_ADRS_OFFSET_2 0x00025000
|
|
#define MOT_TSEC_DEV_NAME "mottsec"
|
|
#define MOT_TSEC_DEV_NAME_LEN 8
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __INCmotTsecEndh */
|