196 lines
5.4 KiB
C
196 lines
5.4 KiB
C
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/* cavPow.h - Cavium Support Routines */
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/*
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* Copyright (c) 2011 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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modification history
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--------------------
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01j,09dec11,x_f add defines for OcteonII CN68xx
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01i,07jul11,rlg Setup for SDK TYPEDEFS only
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01h,10jun11,d_c Restore Cavium headers to original form, before splitting
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struct defs to separate headers
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01g,07feb11,d_c Fix defect WIND00253754. Add define for number of POW groups
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01f,28jan11,d_c Fix compile warning
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01e,20oct10,d_c Include SDK data types directly from SDK
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01d,05oct10,d_c Change ull to ULL to be Diab compatible
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01c,28sep10,d_c Make cav header names consistent.
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01b,13aug10,d_c Add interface elements to support vxbOcteonEnd.c
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01a,26jul10,rlg Written
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*/
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/*
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DESCRIPTION
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This file declares macros, typedefs, and prototypes for general,
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non-device-specific access routines for Cavium hardware.
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*/
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#ifndef __INCcavPowh
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#define __INCcavPowh
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#include <arch/mips/private/cavSdkDrvInclude.h>
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#define CAV_INCLUDE_TYPEDEFS_ONLY
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#include CAV_SDK_DRV_INCLUDE(cvmx-version.h)
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#include CAV_SDK_DRV_INCLUDE(cvmx-abi.h)
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#include CAV_SDK_DRV_INCLUDE(cvmx-utils.h)
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#include CAV_SDK_DRV_INCLUDE(cvmx-csr-enums.h)
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#include CAV_SDK_DRV_INCLUDE(cvmx-packet.h)
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#include CAV_SDK_DRV_INCLUDE(cvmx-pow-defs.h)
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#include CAV_SDK_DRV_INCLUDE(cvmx-sso-defs.h)
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#include <arch/mips/cavWqe.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define CAV_POW_BASE_ADDR 0x8001670000000000ULL
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#define CAV_POW_NUM_GROUPS 16
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#define CAV_POW_PP_GRP_MSK0_OFF 0x0
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#define CAV_POW_PP_GRP_MSKX_SP 0x8
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#define CAV_POW_WQ_INT_THR0_OFF 0x80
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#define CAV_POW_WQ_INT_THRX_SP 0x8
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#define CAV_POW_WQ_INT_CNT0_OFF 0x100
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#define CAV_POW_WQ_INT_CNTX_SP 0x8
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#define CAV_POW_QOS_THR0_OFF 0x180
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#define CAV_POW_QOS_THRX_SP 0x8
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#define CAV_POW_QOS_RND0_OFF 0x1C0
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#define CAV_POW_QOS_RNDX_SP 0x8
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#define CAV_POW_WQ_INT_OFF 0x200
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#define CAV_POW_WQ_INT_PC_OFF 0x208
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#define CAV_POW_NW_TIM_OFF 0x210
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#define CAV_POW_ECC_ERR_OFF 0x218
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#define CAV_POW_NOS_CNT_OFF 0x228
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#define CAV_POW_PF_RST_MSK_OFF 0x230
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#define CAV_POW_IQ_INT_OFF 0x238
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#define CAV_POW_IQ_INT_EN_OFF 0x240
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#define CAV_POW_WS_PC0_OFF 0x280
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#define CAV_POW_WS_PCX_SP 0x8
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#define CAV_POW_WA_PC0_OFF 0x300
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#define CAV_POW_WA_PCX_SP 0x8
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#define CAV_POW_IQ_CNT0_OFF 0x340
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#define CAV_POW_IQ_CNTX_SP 0x8
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#define CAV_POW_WA_COM_PC_OFF 0x380
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#define CAV_POW_IQ_COM_CNT_OFF 0x388
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#define CAV_POW_TS_PC_OFF 0x390
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#define CAV_POW_DS_PC_OFF 0x398
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#define CAV_POW_IQ_THR0_OFF 0x3A0
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#define CAV_POW_IQ_THRX_SP 0x8
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#define CAV_POW_BIST_STAT_OFF 0x3F8
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#define CAV_SSO_NUM_GROUPS 64
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#define CAV_SSO_WQ_INT 0x8001670000001000ULL
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#define CAV_SSO_WQ_IQ_DIS 0x8001670000001010ULL
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#define CAV_SSO_WQ_INT_PC 0x8001670000001020ULL
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#define CAV_SSO_PPX_GRP_MSK(i) (0x8001670000006000ULL + (i) * 8)
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#define CAV_SSO_WQ_INT_THRX(i) (0x8001670000007000ULL + (i) * 8)
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#define CAV_SSO_WQ_INT_CNTX(i) (0x8001670000008000ULL + (i) * 8)
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#define CAV_SSO_IQ_CNTX(i) (0x8001670000009000ULL + (i) * 8)
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#define CAV_SSO_IQ_THRX(i) (0x800167000000a000ULL + (i) * 8)
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#define CAV_SSO_GRPX_INT(i) (0x8001670020000400ULL + (i) * 0x10000ULL)
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#define CAV_SSO_GRPX_INT_THR(i) (0x8001670020000500ULL + (i) * 0x10000ULL)
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/* ACCESS MACROS */
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#define CAV_POW_PP_GRP_MSKX(group) \
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(CAV_POW_BASE_ADDR + (CAV_POW_PP_GRP_MSK0_OFF + \
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((group & 15) * CAV_POW_PP_GRP_MSKX_SP)))
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#if _BYTE_ORDER == _BIG_ENDIAN
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#define CAV_POW_PP_GRP_MASK 0x000000000000ffffULL
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#define CAV_POW_PP_GRP_MSK_SHIFT(x) (x)
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#else
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#define CAV_POW_PP_GRP_MASK 0xffff000000000000ULL
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#define CAV_POW_PP_GRP_MSK_SHIFT(x) (x) << 48
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#endif /* _BYTE_ORDER */
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#define CAV_POW_WQ_INT_PC \
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(CAV_POW_BASE_ADDR + CAV_POW_WQ_INT_PC_OFF)
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#define CAV_POW_WQ_INT \
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(CAV_POW_BASE_ADDR + CAV_POW_WQ_INT_OFF)
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#define CAV_POW_WQ_INT_THRX(group) \
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(CAV_POW_BASE_ADDR + CAV_POW_WQ_INT_THR0_OFF \
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+ (group & 15) * CAV_POW_WQ_INT_THRX_SP)
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#define CAV_POW_TAG_TYPE_ORDERED CVMX_POW_TAG_TYPE_ORDERED
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#define CAV_POW_TAG_TYPE_ATOMIC CVMX_POW_TAG_TYPE_ATOMIC
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#define CAV_POW_TAG_TYPE_NULL CVMX_POW_TAG_TYPE_NULL
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#define CAV_POW_TAG_TYPE_NULL_NULL CVMX_POW_TAG_TYPE_NULL_NULL
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/* typedefs */
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typedef enum
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{
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CAV_POW_WAIT = 1,
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CAV_POW_NO_WAIT = 0
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} CAV_POW_WAIT_T;
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typedef cvmx_pow_wq_int_thrx_t CAV_POW_WQ_INT_THRX_T;
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typedef cvmx_pow_wq_int_t CAV_POW_WQ_INT_T;
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#if (OCTEON_MODEL == OCTEON_CN68XX)
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typedef cvmx_sso_wq_int_thrx_t CAV_SSO_WQ_INT_THRX_T;
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typedef cvmx_sso_wq_int_t CAV_SSO_WQ_INT_T;
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#endif /* (OCTEON_MODEL == OCTEON_CN68XX) */
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#if (OCTEON_SDK_VERSION_NUM >= 301010547)
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typedef cvmx_sso_wq_int_pc_t CAV_SSO_WQ_INT_PC_T;
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typedef cvmx_sso_grpx_int_thr_t CAV_SSO_GRPX_INT_THR_T;
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typedef cvmx_sso_grpx_int_t CAV_SSO_GRPX_INT_T;
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#endif
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/* functions */
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CAV_WQE_T * cavPowWorkRequestSync
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(
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CAV_POW_WAIT_T wait
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);
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CAV_WQE_T * cavSsoWorkRequestGrpSyncNocheck
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(
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unsigned lgrp,
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CAV_POW_WAIT_T wait
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);
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void cavPowGroupMaskSet
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(
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uint64_t core,
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uint64_t mask
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);
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int cavPowNumEntriesGet(void);
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STATUS cavPowHelperSsoInitialize
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(
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int wqeEntries
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);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCcavPowh */
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