126 lines
5.0 KiB
C
126 lines
5.0 KiB
C
/* vmLibCommon.h - Virtual Memory Attribute Information */
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/*
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* Copyright (c) 1998-2005 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01g,02oct06,jmg As part of Defect #WIND00041347 repclace typedef enum
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mmu_attributes will all #defines
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01f,02sep05,pch add IS_VALID_CACHEABLE macro for SPR 110099
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01e,22oct04,pch SPR 102912: add #ifndef _ASMLANGUAGE
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01d,13sep04,dtr Use SPL7 for NO_BLOCK attribute.
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01c,10jun04,pcs Rename MMU_ATTR_CACHE_IO MMU_ATTR_CACHE_GUARDED
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01b,14may04,pcs Add MMU_ATTR_SPL_[4-7].
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01a,28jan04,gls created from mmuAttr.h
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*/
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#ifndef __INCvmLibCommonh
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#define __INCvmLibCommonh
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* includes */
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/* defines */
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#define MMU_ATTR_SUP_RO (MMU_ATTR_PROT_SUP_READ)
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#define MMU_ATTR_SUP_RW (MMU_ATTR_PROT_SUP_READ | MMU_ATTR_PROT_SUP_WRITE)
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#define MMU_ATTR_SUP_EXE (MMU_ATTR_PROT_SUP_READ | MMU_ATTR_PROT_SUP_EXE)
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#define MMU_ATTR_SUP_RWX (MMU_ATTR_SUP_RW | MMU_ATTR_PROT_SUP_EXE)
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#define MMU_ATTR_USR_RO (MMU_ATTR_PROT_USR_READ)
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#define MMU_ATTR_USR_RW (MMU_ATTR_PROT_USR_READ | MMU_ATTR_PROT_USR_WRITE)
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#define MMU_ATTR_USR_EXE (MMU_ATTR_PROT_USR_READ | MMU_ATTR_PROT_USR_EXE)
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#define MMU_ATTR_USR_RWX (MMU_ATTR_USR_RW | MMU_ATTR_PROT_USR_EXE)
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#define MMU_ATTR_SUP_TEXT (MMU_ATTR_SUP_EXE)
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#define MMU_ATTR_SUP_TEXT_W (MMU_ATTR_SUP_RWX)
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#define MMU_ATTR_SUP_DATA (MMU_ATTR_SUP_RW)
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#define MMU_ATTR_SUP_DATA_RO (MMU_ATTR_SUP_RO)
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#define MMU_ATTR_USR_TEXT (MMU_ATTR_USR_EXE | MMU_ATTR_SUP_TEXT)
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#define MMU_ATTR_USR_TEXT_W (MMU_ATTR_USR_RWX | MMU_ATTR_SUP_TEXT_W)
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#define MMU_ATTR_USR_DATA (MMU_ATTR_USR_RW | MMU_ATTR_SUP_DATA)
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#define MMU_ATTR_USR_DATA_RO (MMU_ATTR_USR_RO | MMU_ATTR_SUP_DATA_RO)
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#define MMU_ATTR_SUP_IO (MMU_ATTR_SUP_RW | MMU_ATTR_CACHE_IO)
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#define MMU_ATTR_SUP_IO_RO (MMU_ATTR_SUP_RO | MMU_ATTR_CACHE_IO)
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#define MMU_ATTR_USR_IO (MMU_ATTR_USR_RW | MMU_ATTR_SUP_IO)
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#define MMU_ATTR_USR_IO_RO (MMU_ATTR_USR_RO | MMU_ATTR_SUP_IO_RO)
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/* Special attribute rename */
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#define MMU_ATTR_NO_BLOCK (MMU_ATTR_SPL_7)
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/* typedefs */
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#ifndef _ASMLANGUAGE
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typedef unsigned int MMU_ATTR;
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#endif /* _ASMLANGUAGE */
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#define MMU_ATTR_MSK_ID_MSK 0x000000e0 /* Distinguishing Bits Mask */
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#define MMU_ATTR_PROT_MSK 0x0000003f /* Protection Mask */
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#define MMU_ATTR_PROT_SUP_MSK 0x00000007 /* Sup Mode protection bits */
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#define MMU_ATTR_PROT_SUP_READ 0x00000001 /* Supervisor -- Read */
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#define MMU_ATTR_PROT_SUP_WRITE 0x00000002 /* Supervisor -- Write */
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#define MMU_ATTR_PROT_SUP_EXE 0x00000004 /* Supervisor -- Execute */
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#define MMU_ATTR_PROT_USR_MSK 0x00000038 /* User Mode protection bits */
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#define MMU_ATTR_PROT_USR_READ 0x00000008 /* User -- Read */
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#define MMU_ATTR_PROT_USR_WRITE 0x00000010 /* User -- Write */
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#define MMU_ATTR_PROT_USR_EXE 0x00000020 /* User -- Execute */
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#define MMU_ATTR_VALID_MSK 0x00000040 /* Valid Mask */
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#define MMU_ATTR_VALID_NOT 0x00000000 /* Valid -- Not Valid */
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#define MMU_ATTR_VALID 0x00000040 /* Valid -- Valid */
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#define MMU_ATTR_CACHE_MSK 0x00000f80 /* Cache Mask */
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#define MMU_ATTR_CACHE_OFF 0x00000080 /* Cache -- Turned off */
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#define MMU_ATTR_CACHE_COPYBACK 0x00000100 /* Cache -- Copy/Writeback */
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#define MMU_ATTR_CACHE_WRITETHRU 0x00000180 /* Cache -- Write through */
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#define MMU_ATTR_CACHE_COHERENCY 0x00000200 /* Cache -- mem coherency */
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#define MMU_ATTR_CACHE_GUARDED 0x00000400 /* Cache -- guarded */
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#define MMU_ATTR_CACHE_DEFAULT 0x00000800 /* Cache -- use default */
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#define MMU_ATTR_SPL_MSK 0x000FF000 /* MMU specific spl attributes */
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#define MMU_ATTR_SPL_0 0x00001000
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#define MMU_ATTR_SPL_1 0x00002000
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#define MMU_ATTR_SPL_2 0x00004000
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#define MMU_ATTR_SPL_3 0x00008000
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#define MMU_ATTR_SPL_4 0x00010000
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#define MMU_ATTR_SPL_5 0x00020000
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#define MMU_ATTR_SPL_6 0x00040000
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#define MMU_ATTR_SPL_7 0x00080000 /* Reserved - used for NO_BLOCK */
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/*
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* In principle, a region in sysPhysMemDesc is cacheable if its mask includes
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* specification of validity and cacheability, and the specifications are:
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* valid
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* and not cache-off
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* and one of copyback, writethrough, or default.
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* Due to the relationships among the OFF, CB, and WT bit values,
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* we check for only CB or DEFAULT.
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*/
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#define IS_VALID_CACHEABLE(mask, attr) \
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( \
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((mask) & MMU_ATTR_VALID_MSK) == MMU_ATTR_VALID_MSK \
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&& ((mask) & MMU_ATTR_CACHE_MSK) == MMU_ATTR_CACHE_MSK \
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&& ((attr) & MMU_ATTR_VALID) == MMU_ATTR_VALID \
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&& ((attr) & (MMU_ATTR_CACHE_COPYBACK | MMU_ATTR_CACHE_DEFAULT)) != 0 \
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)
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/* variable declarations */
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/* function prototypes */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCvmLibCommonh */
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