59 lines
1.1 KiB
C
59 lines
1.1 KiB
C
/* cacheArm926eLib.h - ARM 926E cache library header file */
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/* Copyright 2002-2005 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01d,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
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01c,07dec04,jb Further Palify ARM Aim cache
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01b,11dec03,scm flushing out aim...
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01a,09dec02,jpd created, based on cacheArm946eLib.h
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*/
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#ifndef __INCcacheArm926eLibh
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#define __INCcacheArm926eLibh
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Some cache designs (e.g. Harvard) have D-cache either fully or
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* partially not coherent with I-cache
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*/
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#define ARMCACHE_NOT_COHERENT TRUE
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/*
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* This is a writethrough cache
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*/
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#define ARMCACHE_HAS_WRITETHROUGH TRUE
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/*
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* Does not have a mini-cache
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*/
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#define ARMCACHE_HAS_MINICACHE FALSE
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/*
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* Do not need an Instruction Memory Barrier
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*/
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#define ARMCACHE_NEEDS_IMB FALSE
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#ifndef _ASMLANGUAGE
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IMPORT void cacheArm926eLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
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PHYS_ADDR(virtToPhys) (VIRT_ADDR));
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCcacheArm926eLibh */
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