395 lines
16 KiB
C
395 lines
16 KiB
C
/* dbgPpcLib.h - header file for arch dependent portion of debugger */
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/*
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* Copyright (c) 1995,1997-2002,2004,2005,2008,2010-2011,2016
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* Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01x,20may16,jmp Imported from vxWorks 7 for WB4 debug support:
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Added support for watchpoint width 2,4,8 for PPCE500
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for VxDBG upgrade for WB4 support.
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01w,02dec11,h_k added pc member to DBG_REGS for PPC60x. (WIND00191292)
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01v,03may11,syt Added support for PPC465.
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01u,15nov10,x_z Added support for PPC476.
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01t,29apr10,pad Moved extern C statement after include statements.
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01s,31mar09,dbt Disable hardware breakpoint support for Hypervisor
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Guest OS (WIND00161733).
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01r,28mar05,dtr Add support for 83xx and g2le
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01q,25feb05,pch handle PPC970 hardware breakpoints
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01p,11feb04,elg Add syscall instruction size macro.
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01o,09feb04,elg Remove DBG_SYSCALL_CHECK() definition.
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01n,13jan04,elg Add system call check support.
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01o,02dec02,mil Updated support for PPC85XX.
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01n,02aug02,pcs Add support for PPC85XX and make it the same as PPC603 for
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the present.
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01m,14mar02,pch SPR 74270: make 440 bh types consistent with 5xx/604/860
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01l,23aug01,pch Separate PPC440 from PPC405, cleanup.
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01k,16aug01,pch Add PPC440 support
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01j,30oct00,s_m separated PPC405 support from PPC403
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01i,27oct00,s_m updated for CPU == PPC405F
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01h,25oct00,s_m renamed PPC405 cpu types
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01g,13jun00,alp Added PPC405 Support
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01f,19apr99,zl added support for PPC509 and PPC555
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01e,14oct98,elg added hardware breakpoints for PPC603 and PPC604
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01d,27jul98,elg added hardware breakpoints
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01c,24dec97,dbt modified for new breakpoint scheme.
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01b,24oct95,kdl added DBG_TRACE=FALSE for PPC403; added mod hist.
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01a,14feb95,yao created.
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*/
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#ifndef __INCdbgPpcLibh
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#define __INCdbgPpcLibh
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#include "esf.h"
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#include "reg.h"
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#ifndef _ASMLANGUAGE
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#include "dsmLib.h"
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#endif /* _ASMLANGUAGE */
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#include "iv.h"
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#include <vsbConfig.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define BREAK_ESF ESFPPC /* XXX */
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#define DBG_BREAK_INST 0x7fe00008 /* trap 31, 0, 0 */
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#define DBG_SYSCALL_SIZE (sizeof (INSTR) / sizeof (INSTR))
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#ifndef _PPC_MSR_SE
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/*
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* Tell generic code it must simulate single-step using breakpoints.
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* This setting causes wdbDbgArchLib.c to export wdbDbgGetNpc(),
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* and to call wdbDbgTrap() instead of wdbDbgBreakpoint().
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*
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* XXX - PPC4xx have no SE bit in MSR, but do provide an "instruction
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* XXX - completion" debug event which has a similar effect and could
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* XXX - perhaps be used instead of doing this.
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*/
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#define DBG_NO_SINGLE_STEP 1 /* no trace support */
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#endif /* _PPC_MSR_SE */
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/* definition for HID1 register for 601 */
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#define HID1_RUN_MODE(x) (((x)&0x70000000)>>28)
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#define HID1_RUN_NORM
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#define HID1_RUN_UNDEF
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#define HID1_RUN_UNDEF
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/*
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* Set DBG_HARDWARE_BP for CPUs which support hardware breakpoints, and
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* define the breakpoint types.
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*
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* If defined, BRK_INST will be handled by generic code in wdb/wdbBpLib.c
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* and ostool/dbgTaskLib.c. Other breakpoint types are CPU-specific, and
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* are used primarily in wdbDbgArchLib.c. The help text and type-display
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* code in dbgArchLib.c should also match the definitions here.
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*
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* BRK_HARDMASK is used to extract the type from bp_flags. It must be
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* at least large enough to cover all defined types, and must not overlap
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* with BRK_HARDWARE, nor with the flag bits (BP_INSTALLED, BP_HOST, BP_SO,
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* BP_STEP, BP_EVENT) defined in wdb/wdbDbgLib.h.
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*/
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#if (CPU == PPC509) || (CPU == PPC555) || (CPU == PPC603) || \
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(CPU == PPCEC603) || (CPU == PPC604) || (CPU == PPC860)
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#define DBG_HARDWARE_BP 1
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#define BRK_INST 0x0 /* hardware instruction breakpoint */
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#define BRK_RW 0x1 /* hardware data breakpoint for read or write */
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#define BRK_READ 0x2 /* hardware data breakpoint for read */
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#define BRK_WRITE 0x3 /* hardware data breakpoint for write */
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#define DEFAULT_HW_BP BRK_RW /* default hardware breakpoint */
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#define BRK_HARDWARE 0x10 /* hardware breakpoint bit */
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#define BRK_HARDMASK 0x0f /* hardware breakpoint mask */
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#elif (CPU == PPC403)
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#define DBG_HARDWARE_BP 1
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#define BRK_INST 0x0 /* hardware instruction breakpoint */
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#define BRK_DATAW1 0x1 /* data breakpoint for write one byte */
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#define BRK_DATAR1 0x2 /* data breakpoint for read one byte */
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#define BRK_DATARW1 0x3 /* data breakpoint for read/write one byte */
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#define BRK_DATAW2 0x5 /* data breakpoint for write 2 bytes */
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#define BRK_DATAR2 0x6 /* data breakpoint for read 2 bytes */
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#define BRK_DATARW2 0x7 /* data breakpoint for read/write 2 bytes */
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#define BRK_DATAW4 0x9 /* data breakpoint for write 4 bytes */
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#define BRK_DATAR4 0xA /* data breakpoint for read 4 bytes */
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#define BRK_DATARW4 0xB /* data breakpoint for read/write 4 bytes */
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#define BRK_DATAW16 0xD /* data breakpoint for write 16 bytes */
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#define BRK_DATAR16 0xE /* data breakpoint for read 16 bytes */
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#define BRK_DATARW16 0xF /* data breakpoint for read/write 16 bytes */
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#define DEFAULT_HW_BP BRK_DATAW1 /* default hardware breakpoint */
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#define BRK_HARDWARE 0x10 /* hardware breakpoint bit */
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#define BRK_HARDMASK 0x0f /* hardware breakpoint mask */
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#elif ((CPU == PPC405) || (CPU == PPC405F))
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#define DBG_HARDWARE_BP 1
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#define BRK_INST 0x0 /* hardware instruction breakpoint */
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#define BRK_DATAW1 0x1 /* data breakpoint for write one byte */
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#define BRK_DATAR1 0x2 /* data breakpoint for read one byte */
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#define BRK_DATARW1 0x3 /* data breakpoint for read/write one byte */
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#define BRK_DATAW2 0x4 /* data breakpoint for write 2 bytes */
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#define BRK_DATAR2 0x5 /* data breakpoint for read 2 bytes */
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#define BRK_DATARW2 0x6 /* data breakpoint for read/write 2 bytes */
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#define BRK_DATAW4 0x7 /* data breakpoint for write 4 bytes */
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#define BRK_DATAR4 0x8 /* data breakpoint for read 4 bytes */
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#define BRK_DATARW4 0x9 /* data breakpoint for read/write 4 bytes */
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#define BRK_DATAW32 0xA /* data breakpoint for write cache line size */
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#define BRK_DATAR32 0xB /* data breakpoint for read 16 bytes */
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#define BRK_DATARW32 0xC /* data breakpoint for read/write 16 bytes */
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#define DEFAULT_HW_BP BRK_DATAW1 /* default hardware breakpoint */
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#define BRK_HARDWARE 0x10 /* hardware breakpoint bit */
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#define BRK_HARDMASK 0x0f /* hardware breakpoint mask */
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#elif ((CPU == PPC440) || (CPU == PPC85XX) || (CPU == PPC476) || \
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(CPU == PPC465))
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#define DBG_HARDWARE_BP 1
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#define BRK_INST 0x0 /* hardware instruction breakpoint */
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#define BRK_DATARW 0x1 /* data breakpoint for read/write */
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#define BRK_DATAR 0x2 /* data breakpoint for read */
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#define BRK_DATAW 0x3 /* data breakpoint for write */
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#if (CPU == PPC85XX)
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#define _WRS_CONFIG_PPC_E500
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#endif
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#if defined (_WRS_CONFIG_PPC_E500)
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/*
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* PPC_E500 architecture (PPCE500V2 & PPCE500MC) supports setting either:
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* - 2 watchpoints with 1byte access mode using DAC1 & DAC2:
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* Data Address Compare Mode set to exact address compare mode: DAC12M = 00
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* - 1 watchpoint with an access range defined with DAC1 & DAC2:
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* Data Address Compare Mode set to inclusive address range: DAC12M = 10
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*
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* As current VxDBG HW BP infrastructure does not support setting HW BP on
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* an address range, we fake support of 2,4,8 width with the following access
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* types, and the low level implementation does use inclusive address range
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* mode to support those access sizes.
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*/
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#define BRK_DATARW2 0x4 /* data breakpoint for read/write 2 bytes */
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#define BRK_DATAR2 0x5 /* data breakpoint for read 2 bytes */
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#define BRK_DATAW2 0x6 /* data breakpoint for write 2 bytes */
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#define BRK_DATARW4 0x7 /* data breakpoint for read/write 4 bytes */
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#define BRK_DATAR4 0x8 /* data breakpoint for read 4 bytes */
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#define BRK_DATAW4 0x9 /* data breakpoint for write 4 bytes */
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#define BRK_DATARW8 0xA /* data breakpoint for read/write 8 bytes */
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#define BRK_DATAR8 0xB /* data breakpoint for read 8 bytes */
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#define BRK_DATAW8 0xC /* data breakpoint for write 8 bytes */
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#endif
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/* XXX - 440 has 4 IAC registers (each pair usable as a range), and
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* XXX - 2 DAC registers (usable as a range); also DVC, BRT, ICMP,
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* XXX - IRPT, TRAP, and RET events. How much of this to support?
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* XXX - ditto to 85XX, which doesn't have IAC3 and IAC4
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*/
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#define DEFAULT_HW_BP BRK_DATAW /* default hardware breakpoint */
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#define BRK_HARDWARE 0x10 /* hardware breakpoint bit */
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#define BRK_HARDMASK 0x0f /* hardware breakpoint mask */
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#endif /* 509 555 603 EC603 604 860 : 403 : 405 405F : 440 85XX 476 */
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/* End of hardware breakpoint type definitions */
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/* No hardware breakpoint support in Hypervisor Guest OS for now */
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#ifdef _WRS_CONFIG_WRHV_GUEST
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#undef DBG_HARDWARE_BP
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#define DBG_HARDWARE_BP 0
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#endif /* _WRS_CONFIG_WRHV_GUEST */
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#if DBG_HARDWARE_BP
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#ifndef _ASMLANGUAGE
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/*
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* The DBG_REGS structure specifies the values to be
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* loaded into the hardware breakpoint registers.
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*/
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typedef struct
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{
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#if ((CPU == PPC509) || (CPU == PPC555) || (CPU == PPC860))
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UINT32 cmpa; /* comparator A value register */
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UINT32 cmpb; /* comparator B value register */
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UINT32 cmpc; /* comparator C value register */
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UINT32 cmpd; /* comparator D value register */
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UINT32 counta; /* breakpoint counter value register A */
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UINT32 countb; /* breakpoint counter value register B */
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UINT32 cmpe; /* comparator E value register */
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UINT32 cmpf; /* comparator F value register */
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UINT32 cmpg; /* comparator G value register */
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UINT32 cmph; /* comparator H value register */
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UINT32 lctrl1; /* load/store support comparators control reg */
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UINT32 lctrl2; /* load/store support AND-OR control register */
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UINT32 ictrl; /* instruction support control register */
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UINT32 bar; /* breakpoint address register */
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#elif CPU == PPC603 || CPU == PPCEC603 || CPU == PPC604 || CPU == PPC970
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# if CPU != PPC970
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UINT32 iabr; /* instruction address breakpoint register */
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# endif /* !PPC_970 */
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# if CPU == PPC604 || CPU == PPC970
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UINT32 dabr; /* data address breakpoint register */
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UINT32 dar; /* data address register */
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# endif /* 604 || 970 */
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#if (defined PPC_83xx || defined (PPC_g2le))
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UINT32 iabr2;
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UINT32 ibcr;
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UINT32 dabr;
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UINT32 dabr2;
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UINT32 dbcr;
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UINT32 dar; /* data address register */
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#endif /* PPC_83xx | PPC_g2le */
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UINT32 pc; /* program counter at the time of HW break */
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#elif (CPU == PPC403)
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UINT32 dbcr; /* debug control register */
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UINT32 dbsr; /* debug status register */
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UINT32 dac1; /* data address compare register 1 */
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UINT32 dac2; /* data address compare register 2 */
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UINT32 iac1; /* instruction address compare register 1 */
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UINT32 iac2; /* instruction address compare register 2 */
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UINT32 msr; /* machine state register */
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#elif ((CPU == PPC405) || (CPU == PPC405F) || (CPU == PPC440) || \
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(CPU == PPC85XX) || (CPU == PPC476) || (CPU == PPC465))
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UINT32 dbcr0; /* debug control register 0 */
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UINT32 dbcr1; /* debug control register 1 */
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# if ((CPU == PPC440) || (CPU == PPC85XX) || (CPU == PPC476) || (CPU == PPC465))
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UINT32 dbcr2; /* debug control register 2 */
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# endif /* CPU == PPC440, PPC85XX, PPC476, PPC465 */
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# if ((CPU == PPC440) || (CPU == PPC476) || (CPU == PPC465))
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UINT32 dbdr; /* debug data register */
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# endif /* CPU == PPC440, PPC476 */
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UINT32 dbsr; /* debug status register */
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UINT32 dac1; /* data address compare register 1 */
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UINT32 dac2; /* data address compare register 2 */
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UINT32 iac1; /* instruction address compare register 1 */
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UINT32 iac2; /* instruction address compare register 2 */
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# if (CPU != PPC85XX)
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UINT32 iac3; /* instruction address compare register 3 */
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UINT32 iac4; /* instruction address compare register 4 */
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# endif /* CPU != PPC85XX */
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UINT32 msr; /* machine state register */
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#endif /* 509 555 860 : 603 EC603 604 : 403 : 405 405F 440 85XX 476*/
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} DBG_REGS;
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/* Prototypes for hardware breakpoint register access functions */
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# if ((CPU == PPC509) || (CPU == PPC555) || (CPU == PPC860))
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extern void dbgCmpaSet (int value);
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extern void dbgCmpbSet (int value);
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extern void dbgCmpcSet (int value);
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extern void dbgCmpdSet (int value);
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extern void dbgCmpeSet (int value);
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extern void dbgCmpfSet (int value);
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extern void dbgLctrl1Set (int value);
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extern void dbgLctrl2Set (int value);
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extern void dbgIctrlSet (int value);
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extern int dbgCmpaGet (void) ;
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extern int dbgCmpbGet (void) ;
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extern int dbgCmpcGet (void) ;
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extern int dbgCmpdGet (void) ;
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extern int dbgCmpeGet (void) ;
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extern int dbgCmpfGet (void) ;
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extern int dbgLctrl1Get (void) ;
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extern int dbgLctrl2Get (void) ;
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extern int dbgIctrlGet (void) ;
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# elif CPU == PPC603 || CPU == PPCEC603 || CPU == PPC604 || CPU == PPC970
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# if CPU != PPC970
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extern void wdbDbgIabrSet (int value);
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extern int wdbDbgIabrGet (void);
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# endif /* !PPC_970 */
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# if CPU == PPC604 || CPU == PPC970
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extern void wdbDbgDabrSet (int value);
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extern int wdbDbgDabrGet (void);
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extern int wdbDbgDarGet (void);
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# endif /* 604 || 970 */
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# if (defined (PPC_83xx) || defined (PPC_g2le))
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extern int wdbDbgDarGet (void);
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extern void wdbDbgIabr2Set (int value);
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extern int wdbDbgIabr2Get (void);
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extern void wdbDbgIbcrSet (int value);
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extern int wdbDbgIbcrGet (void);
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extern void wdbDbgDabrSet (int value);
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extern int wdbDbgDabrGet (void);
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extern void wdbDbgDabr2Set (int value);
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extern int wdbDbgDabr2Get (void);
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extern void wdbDbgDbcrSet (int value);
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extern int wdbDbgDbcrGet (void);
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# endif /* PPC_83xx || PPC_g2le */
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# elif (CPU == PPC403)
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extern void wdbDbgDbcrSet (int value);
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extern int wdbDbgDbcrGet (void);
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extern void wdbDbgDbsrSet (int value);
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extern int wdbDbgDbsrGet (void);
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extern void wdbDbgDac1Set (int value);
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extern int wdbDbgDac1Get (void);
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extern void wdbDbgDac2Set (int value);
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extern int wdbDbgDac2Get (void);
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extern void wdbDbgIac1Set (int value);
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extern int wdbDbgIac1Get (void);
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extern void wdbDbgIac2Set (int value);
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extern int wdbDbgIac2Get (void);
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# elif ((CPU == PPC405) || (CPU == PPC405F) || (CPU == PPC440) || \
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(CPU == PPC85XX) || (CPU == PPC476) || (CPU == PPC465))
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extern void wdbDbgDbcr0Set (int value);
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extern int wdbDbgDbcr0Get (void);
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extern void wdbDbgDbcr1Set (int value);
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extern int wdbDbgDbcr1Get (void);
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# if ((CPU == PPC440) || (CPU == PPC85XX) || (CPU == PPC476) || (CPU == PPC465))
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extern void wdbDbgDbcr2Set (int value);
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extern int wdbDbgDbcr2Get (void);
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# endif /* CPU == PPC440, PPC85XX, PPC476, PPC465 */
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# if ((CPU == PPC440) || (CPU == PPC476) || (CPU == PPC465))
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extern void wdbDbgDbdrSet (int value);
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extern int wdbDbgDbdrGet (void);
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# endif /* (CPU == PPC440, PPC476, PPC465) */
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extern void wdbDbgDbsrSet (int value);
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extern int wdbDbgDbsrGet (void);
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extern void wdbDbgDac1Set (int value);
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extern int wdbDbgDac1Get (void);
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extern void wdbDbgDac2Set (int value);
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extern int wdbDbgDac2Get (void);
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extern void wdbDbgIac1Set (int value);
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extern int wdbDbgIac1Get (void);
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extern void wdbDbgIac2Set (int value);
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extern int wdbDbgIac2Get (void);
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# if (CPU != PPC85XX)
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extern void wdbDbgIac3Set (int value);
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extern int wdbDbgIac3Get (void);
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extern void wdbDbgIac4Set (int value);
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extern int wdbDbgIac4Get (void);
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# endif /* CPU != PPC85XX */
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# endif /* 509 555 860 : 603 EC603 604 : 403 : 405 405F 440 85XX 476*/
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#endif /* _ASMLANGUAGE */
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#endif /* DBG_HARDWARE_BP */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCdbgPpcLibh */
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