185 lines
6.2 KiB
C
185 lines
6.2 KiB
C
/* dbgMipsLib.h - MIPS debugger header */
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/*
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* Copyright 1992, 1993, 1996-1999, 2001, 2003-2005, 2008-2009
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*, 2010 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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* This file has been developed or significantly modified by the
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* MIPS Center of Excellence Dedicated Engineering Staff.
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* This notice is as per the MIPS Center of Excellence Master Partner
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* Agreement, do not remove this notice without checking first with
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* WR/Platforms MIPS Center of Excellence engineering management.
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*/
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/*
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modification history
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--------------------
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01p,29apr10,pad Moved extern C statement after include statements.
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01o,27aug09,pch CQ159556: remove MIPS16
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01n,29oct08,rlg WIND00115621 - hw breakpoints in user space - add define for
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watchHi bits
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01m,23aug05,rlg modifications for MIPS 32/64 compliant cores - hw breakpoints
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01l,01mar04,pes Add definition of DBG_SYSCALL_SIZE.
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01k,12may03,pes PAL conditional compilation cleanup. Phase 2.
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01j,16jul01,ros add CofE comment
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01i,08sep99,myz added a few macros for CW4000_16
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01h,17mar98,dbt added definition of DBG_CRET (no cret() support).
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01g,30dec97,dbt modified for new breakpoint scheme
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01f,15jul96,kkk added R4650 support
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01e,27sep93,cd added R4000 support, including hardware breakpoint.
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01d,25jul93,caf removed definition of DBG_TT. tt() is now supported.
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01c,05aug93,jwt removed DBG_SAVE structure - not used; copyright 1993.
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01b,22sep92,rrr added support for c++
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01a,05may92,yao written based on sparc/dbgLib.c.
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*/
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#ifndef __INCdbgMipsLibh
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#define __INCdbgMipsLibh
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#include "dsmLib.h"
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#include "iv.h"
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#include "esf.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define DBG_TRAP_NUM IV_BP_VEC
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#define DBG_BREAK_INST 0x0000000d
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#define DBG_NO_SINGLE_STEP 1 /* no single step support */
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#define DBG_CRET FALSE /* no cret support */
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#define DBG_BREAK_INST 0x0000000d
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#define DBG_SYSCALL_SIZE 1
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#define DBG_HARDWARE_BP 1 /* support of hardware breakpoint */
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/*
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* modifications for MIPS 32/64 compliant cores - hw breakpoints
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*/
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#define MAX_WATCH 8 /* # of bp regs for 32/64 compliancy */
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/*
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* offsets for indexing into the watch array
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*/
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#define DBG_WATCHLO_0 0
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#define DBG_WATCHHI_0 DBG_WATCHLO_0 + _WRS_INT_REGISTER_SIZE
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#define DBG_WATCHLO_1 DBG_WATCHHI_0 + _WRS_INT_REGISTER_SIZE
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#define DBG_WATCHHI_1 DBG_WATCHLO_1 + _WRS_INT_REGISTER_SIZE
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#define DBG_WATCHLO_2 DBG_WATCHHI_1 + _WRS_INT_REGISTER_SIZE
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#define DBG_WATCHHI_2 DBG_WATCHLO_2 + _WRS_INT_REGISTER_SIZE
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#define DBG_WATCHLO_3 DBG_WATCHHI_2 + _WRS_INT_REGISTER_SIZE
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#define DBG_WATCHHI_3 DBG_WATCHLO_3 + _WRS_INT_REGISTER_SIZE
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#define DBG_WATCHLO_4 DBG_WATCHHI_3 + _WRS_INT_REGISTER_SIZE
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#define DBG_WATCHHI_4 DBG_WATCHLO_4 + _WRS_INT_REGISTER_SIZE
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#define DBG_WATCHLO_5 DBG_WATCHHI_4 + _WRS_INT_REGISTER_SIZE
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#define DBG_WATCHHI_5 DBG_WATCHLO_5 + _WRS_INT_REGISTER_SIZE
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#define DBG_WATCHLO_6 DBG_WATCHHI_5 + _WRS_INT_REGISTER_SIZE
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#define DBG_WATCHHI_6 DBG_WATCHLO_6 + _WRS_INT_REGISTER_SIZE
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#define DBG_WATCHLO_7 DBG_WATCHHI_6 + _WRS_INT_REGISTER_SIZE
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#define DBG_WATCHHI_7 DBG_WATCHLO_7 + _WRS_INT_REGISTER_SIZE
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/*
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* offsets for wdbRegisterType
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*/
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#define WDB_REGTYPE_0 0
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#define WDB_REGTYPE_1 WDB_REGTYPE_0 + 4 /* add 32 bit offset */
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#define WDB_REGTYPE_2 WDB_REGTYPE_1 + 4 /* to each location */
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#define WDB_REGTYPE_3 WDB_REGTYPE_2 + 4
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#define WDB_REGTYPE_4 WDB_REGTYPE_3 + 4
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#define WDB_REGTYPE_5 WDB_REGTYPE_4 + 4
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#define WDB_REGTYPE_6 WDB_REGTYPE_5 + 4
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#define WDB_REGTYPE_7 WDB_REGTYPE_6 + 4
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#ifndef _ASMLANGUAGE
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typedef struct
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{
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/*
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* new struct for mips32/64 compliant hw break points
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* can have up to max of 8 register pairs
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*/
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struct _watch
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{
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_RType watchLo_reg; /* watch low register */
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UINT32 watchHi_reg; /* watch high register */
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}watch[MAX_WATCH];
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/*
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* special defines for non compliant hw break points
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* allows old code to work
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*/
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#define watchLo watch[0].watchLo_reg
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#define watchHi watch[0].watchHi_reg
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UINT32 cause; /* cause register */
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/*
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* new for compliant hw break points
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*/
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INSTR *epc;
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VOID *badVaddr;
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} DBG_REGS;
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/* for R4650 */
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#define iWatch watchLo
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#define dWatch watchHi
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#endif /* _ASMLANGUAGE */
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#define BRK_INST 0x0 /* hardware instruction breakpoint */
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#define BRK_WRITE 0x1 /* hardware data breakpoint for write */
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#define BRK_READ 0x2 /* hardware data breakpoint for read */
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#define BRK_RW 0x3 /* hardware data breakpoint for read/write */
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#define WDB_BRK_INST 0x4 /* hardware instruction type watch reg for */
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/* mips 32/64 compliant hardware */
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#define WDB_BRK_DATA 0x3 /* hardware data type watch regs for */
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/* mips 32/64 compliant hardware */
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#define WDB_BRK_BOTH 0x7 /* both data and instruction type reg */
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/* for mips 32/64 compliant */
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#define WDB_REG_CHK 0x80000000 /* mask for msb - used to determine */
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/* if more watchLo and watchHi present */
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#define WDB_REG_WP_CLR 0xffbfffff /* mask for watch point bit in cause reg */
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#define DEFAULT_HW_BP BRK_RW /* default hardware breakpoint */
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#define BRK_HARDWARE 0x10 /* hardware breakpoint bit */
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#define BRK_HARDMASK 0x03 /* hardware breakpoint mask */
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/* definition of watch hi bits */
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#define WATCHHI_MBIT 0x80000000 /* more registers are defined */
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#define WATCHHI_GBIT 0x40000000 /* global bit when set match */
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/* address in any address space */
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#define WATCHHI_IBIT 0x00000004 /* set when instr addr match */
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#define WATCHHI_RBIT 0x00000002 /* set when read addr match */
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#define WATCHHI_WBIT 0x00000001 /* set when write addr match */
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/* also used to clear the bit */
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#define WATCHHI_BITCA 0x00000007 /* clear all bits */
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#define WATCHHI_ASID_MASK 0x00ff0000 /* mask to get asid bits */
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#define WATCHHI_ASID_SHFT 16 /* shift value to get to asid */
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#ifndef _ASMLANGUAGE
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#define WDB_CTX_LOAD(pRegs) _wdbDbgCtxLoad (pRegs)
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#define WDB_CTX_SAVE(pRegs) _wdbDbgCtxSave (pRegs)
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extern void _wdbDbgCtxLoad();
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extern int _wdbDbgCtxSave();
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCdbgMipsLibh */
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