431 lines
16 KiB
C
431 lines
16 KiB
C
/* vxbIaHpetTimer.h - header for the Intel High Precision Event Timer (HPET) */
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/*
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* Copyright (c) 2011, 2013, 2014 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01i,31jan14,jb VXW6-1845 - Error in HPET reading
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01h,28jan14,jb VXW6-25700 - patch for WIND00406770 does not fix the problem
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in aux timer
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01g,25apr13,rbc WIND00414401 - Changes to support Unified BSP.
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01f,18mar13,jb WIND00406770 - iaHpetTimerInt() -> wrong calculation of next
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timeout
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01e,07oct11,sem WIND00310639 - Remove timer drift. Revise oneshot API.
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01d,02aug11,sem Fix HPET interrupts - WIND00287725
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01c,22jul11,sem Update timestamp name define
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01b,14jul11,sem Update 64-bit counter read
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01a,05may11,sem initial version
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*/
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#ifndef __INCvxbIaHpetTimerh
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#define __INCvxbIaHpetTimerh
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* IA HPET - High Precision Event Timers
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*
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* On IA platforms this gives us a
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* 64-bit free running up-counter for Time Stamping Applications.
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*
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* This provides a time-base that is insensitive to clock frequency
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* drifts on individual CPU's on an N-way MP system.
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*/
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#define IA_TIMESTAMP_NAME "iaTimestamp"
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#ifndef IA_HPET_TIMER_NAME
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#define IA_HPET_TIMER_NAME "iaHpetTimerDev"
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#endif /* IA_HPET_TIMER_NAME */
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#define IA_HPET_TIMER_CLK_FREQ 14318179
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/* HPET timer IDs */
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#define IA_HPET_TIMER0 0x0 /* Timer 0 Id */
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#define IA_HPET_TIMER1 0x1 /* Timer 1 Id */
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#define IA_HPET_TIMER2 0x2 /* Timer 2 Id */
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#define IA_HPET_TIMER3 0x3 /* Timer 3 Id */
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#define IA_HPET_TIMER4 0x4 /* Timer 4 Id */
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#define IA_HPET_TIMER5 0x5 /* Timer 5 Id */
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#define IA_HPET_TIMER6 0x6 /* Timer 6 Id */
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#define IA_HPET_TIMER7 0x7 /* Timer 7 Id */
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#define IA_HPET_TIMER_MAX 0x8 /* Max timer Ids */
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/* HPET timer operational modes */
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#ifdef _WRS_CONFIG_PWR_MGMT
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/* Maintain Power Mgmt functionality */
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#define IA_HPET_TIMER_MODE_PERIODIC 0x00 /* Periodic timer */
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#define IA_HPET_TIMER_MODE_ONESHOT32 0x01 /* 32-bit one-shot timer */
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#define IA_HPET_TIMER_MODE_ONESHOT64 0x02 /* 64-bit one-shot timer */
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#else
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#define IA_HPET_TIMER_MODE_PERIODIC 0x01 /* Periodic timer */
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#define IA_HPET_TIMER_MODE_HW_PERIODIC 0x03 /* Timer supports H/W periodic */
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/* mode */
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#define IA_HPET_TIMER_MODE_ONESHOT32 0x04 /* 32-bit one-shot timer */
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#define IA_HPET_TIMER_MODE_ONESHOT64 0x08 /* 64-bit one-shot timer */
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#endif /* _WRS_CONFIG_PWR_MGMT */
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/* interrupt routing for HPET comparators */
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#define INT_NUM_IA_HPET_TIMER0 0x14 /* Timer 0 interrupt */
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#define INT_NUM_IA_HPET_TIMER1 0x15 /* Timer 1 interrupt */
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#define INT_NUM_IA_HPET_TIMER2 0x16 /* Timer 2 interrupt */
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#define INT_NUM_IA_HPET_TIMER3 0x17 /* Timer 3 interrupt */
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#define INT_NUM_IA_HPET_TIMER4 0x18 /* Timer 4 interrupt */
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#define INT_NUM_IA_HPET_TIMER5 0x19 /* Timer 5 interrupt */
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#define INT_NUM_IA_HPET_TIMER6 0x1A /* Timer 6 interrupt */
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#define INT_NUM_IA_HPET_TIMER7 0x1B /* Timer 7 interrupt */
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/* The HPET LPC Bridge function resides in PCI Device:31, Function:0 */
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#define LPC_BUSNO 0x00
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#define LPC_DEVNO 0x1F
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#define LPC_FUNCNO 0x00
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#define LPC_DID_6300ESB 0x25A1
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#define LPC_DID_ICH5 0x24D0
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#define LPC_GEN_CNTRL 0xD0 /* 6300ESB ICH General Control */
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/* Reg */
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#define LPC_RCBA_REG 0xF0 /* ICH7 Root Complex Base Addr */
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/* Reg */
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#define RCBA_REG_BASE 1
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#define RCBA_ADDR_MSK 0xFFFFC000 /* ICH7 RCBA Address Mask */
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#define RCBA_ADDR_ENBL 0x00000001 /* ICH7 RCBA Enable Bit */
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#define RCBA_MEM_ADDR_RNG 0x4000 /* ICH7 RCBA Address Block */
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#define IA_HPETTC_REG_OFFSET 0x00003404 /* ICH7 HPTC Register Offset */
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#define IA_HPETTC_REG_MSK 0xFFFFFFFE /* ICH7 HPTC Register Mask */
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#define IA_HPETTC_ADDR_ENBL 0x00000080 /* ICH7 HPTC Address Enable Bit */
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/*
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* This bit enables the ICH to decode the High Performance Event Timer
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* memory Address Range...
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*
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* The registers associated with these timers are mapped to memory space
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* much like the I/O APIC. The timer register space is 1024 bytes.
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*/
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#define IA_HPET_ADDR_ENABLE 0x00020000
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/*
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* 1 of 4 possible memory address ranges for the High Performance
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* Event Timer functionality...
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*/
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#define IA_HPET_ADDR_SEL_MASK 0x00018000
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#define IA_HPET_ADDR_SEL_00 0xFED00000
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#define IA_HPET_ADDR_SEL_01 0xFED01000
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#define IA_HPET_ADDR_SEL_02 0xFED02000
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#define IA_HPET_ADDR_SEL_03 0xFED03000
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#define IA_HPET_MEM_ADDR_RNG 0x4000
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/* HPET Memory-mapped Register Offsets */
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/*
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* General Capabilities and ID Register
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* Offset: 000-007h, RO, 64-bit
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*/
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#define IA_HPET_GEN_CAP_OFF 0x0000
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#define IA_HPET_CNTR_PER_CAP_MSK 0xffffffff00000000
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#define IA_HPET_VNDR_ID_CAP_MSK 0x00000000ffff0000
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#define IA_HPET_LEG_RT_CAP_MSK 0x0000000000008000
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#define IA_HPET_CNT_SZ_CAP_MSK 0x0000000000002000
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#define IA_HPET_NUM_TIM_CAP_MSK 0x0000000000001f00
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#define IA_HPET_REV_ID_CAP_MSK 0x00000000000000ff
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/*
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* General Configuration Register
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* Offset: 010-017h, RW, 64-bit
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*/
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#define IA_HPET_GEN_CON_OFF 0x0010
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#define IA_HPET_LEG_RT_CNF_MSK 0x0000000000000002
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#define IA_HPET_EN_CNF_MSK 0x0000000000000001
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/*
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* General Interrupt Status Register
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* Offset: 020-027h, RW, 64-bit
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*/
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#define IA_HPET_INT_STS_OFF 0x0020
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#define IA_HPET_T00_INT_STS_MSK 0x0000000000000001
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#define IA_HPET_T01_INT_STS_MSK 0x0000000000000002
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#define IA_HPET_T02_INT_STS_MSK 0x0000000000000004
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/*
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* Main counter Value Register
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* Offset: 0F0-0F7h, RW, 64-bit
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*/
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#define IA_HPET_MN_CNTR_OFF 0x00F0
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/*
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* Timer Config/Capabilities Registers
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* Offset: 20h, relative to each register
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*/
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#define IA_HPET_TIMER_CONF_OFF 0x0020
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/*
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* Timer Comparator Registers
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* Offset: 20h, relative to each comparator
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*/
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#define IA_HPET_TIMER_COMP_OFF 0x0020
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/*
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* Timer MSI Configuration Registers
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* Offset: 20h, relative to each comparator
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*/
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#define IA_HPET_TIMER_MSI_OFF 0x0020
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/*
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* Timer Config/Capabilities Register
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* Offset: 100-107h, RW, 64-bit
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*
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* Timer Comparator Value Register
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* Offset: 108-10Fh, RW, 64-bit
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*
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* Timer MSI Config Value Register
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* Offset: 110-10Fh, RW, 64-bit
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*/
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#define IA_HPET_T0_CONF_OFF 0x0100
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#define IA_HPET_T0_COMP_OFF 0x0108
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#define IA_HPET_T0_MSI_OFF 0x0110
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#define IA_HPET_T1_CONF_OFF 0x0120
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#define IA_HPET_T1_COMP_OFF 0x0128
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#define IA_HPET_T1_MSI_OFF 0x0130
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#define IA_HPET_T2_CONF_OFF 0x0140
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#define IA_HPET_T2_COMP_OFF 0x0148
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#define IA_HPET_T2_MSI_OFF 0x0150
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#define IA_HPET_T3_CONF_OFF 0x0160
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#define IA_HPET_T3_COMP_OFF 0x0168
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#define IA_HPET_T3_MSI_OFF 0x0170
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#define IA_HPET_T4_CONF_OFF 0x0180
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#define IA_HPET_T4_COMP_OFF 0x0188
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#define IA_HPET_T4_MSI_OFF 0x0180
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#define IA_HPET_T5_CONF_OFF 0x01a0
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#define IA_HPET_T5_COMP_OFF 0x01a8
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#define IA_HPET_T5_MSI_OFF 0x01b0
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#define IA_HPET_T6_CONF_OFF 0x01c0
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#define IA_HPET_T6_COMP_OFF 0x01c8
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#define IA_HPET_T6_MSI_OFF 0x01d0
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#define IA_HPET_T7_CONF_OFF 0x01e0
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#define IA_HPET_T7_COMP_OFF 0x01e8
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#define IA_HPET_T7_MSI_OFF 0x01f0
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/* Timer Config/Capabilities Masks */
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#define IA_HPET_TIMERn_INT_ROUT_CAP_MSK 0xffffffff00000000
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#define IA_HPET_TIMERn_MSI_INT_DEL_CAP_MSK 0x0000000000008000
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#define IA_HPET_TIMERn_MSI_EN_CNF_MSK 0x0000000000004000
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#define IA_HPET_TIMERn_INT_ROUT_CNF_MSK 0x0000000000003e00
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#define IA_HPET_TIMERn_32MODE_CNF_MSK 0x0000000000000100
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#define IA_HPET_TIMERn_VAL_SET_CNF_MSK 0x0000000000000040
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#define IA_HPET_TIMERn_SIZE_CAP_MSK 0x0000000000000020
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#define IA_HPET_TIMERn_PER_INT_CAP_MSK 0x0000000000000010
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#define IA_HPET_TIMERn_TYPE_CNF_MSK 0x0000000000000008
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#define IA_HPET_TIMERn_INT_ENB_CNF_MSK 0x0000000000000004
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#define IA_HPET_TIMERn_INT_TYPE_CNF_MSK 0x0000000000000002
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/*
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* IA Timestamp based off of a 64-bit free running counter
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* using default address range HPET_ADDR_SEL_00 (0xFED00000).
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* This address should be obtained from ACPI tables, however
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* the associated ACPI tables are initialized after the HPET timer
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* driver is instantiated by VxBus.
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*/
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#define IA_HPET_BASE_ADDR (IA_HPET_ADDR_SEL_00)
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#define IA_HPET_REG_BASE (IA_HPET_GEN_CAP_OFF)
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#ifndef _WRS_CONFIG_LP64
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IMPORT UINT vxbIaHpetBaseAddr;
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/* HPET register definitions */
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#define IA_HPET_GEN_CAP (IA_HPET_BASE_ADDR + IA_HPET_GEN_CAP_OFF)
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#define IA_HPET_GEN_CON (IA_HPET_BASE_ADDR + IA_HPET_GEN_CON_OFF)
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#define IA_HPET_INT_STS (IA_HPET_BASE_ADDR + IA_HPET_INT_STS_OFF)
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#define IA_HPET_MN_CNTR (IA_HPET_BASE_ADDR + IA_HPET_MN_CNTR_OFF)
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#define IA_HPET_T0_CONF (IA_HPET_BASE_ADDR + IA_HPET_T0_CONF_OFF)
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#define IA_HPET_T0_COMP (IA_HPET_BASE_ADDR + IA_HPET_T0_COMP_OFF)
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#define IA_HPET_T0_MSI (IA_HPET_BASE_ADDR + IA_HPET_T0_MSI_OFF)
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#define IA_HPET_T1_CONF (IA_HPET_BASE_ADDR + IA_HPET_T1_CONF_OFF)
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#define IA_HPET_T1_COMP (IA_HPET_BASE_ADDR + IA_HPET_T1_COMP_OFF)
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#define IA_HPET_T1_MSI (IA_HPET_BASE_ADDR + IA_HPET_T1_MSI_OFF)
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#define IA_HPET_T2_CONF (IA_HPET_BASE_ADDR + IA_HPET_T2_CONF_OFF)
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#define IA_HPET_T2_COMP (IA_HPET_BASE_ADDR + IA_HPET_T2_COMP_OFF)
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#define IA_HPET_T2_MSI (IA_HPET_BASE_ADDR + IA_HPET_T2_MSI_OFF)
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#define IA_HPET_T3_CONF (IA_HPET_BASE_ADDR + IA_HPET_T3_CONF_OFF)
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#define IA_HPET_T3_COMP (IA_HPET_BASE_ADDR + IA_HPET_T3_COMP_OFF)
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#define IA_HPET_T3_MSI (IA_HPET_BASE_ADDR + IA_HPET_T3_MSI_OFF)
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#define IA_HPET_T4_CONF (IA_HPET_BASE_ADDR + IA_HPET_T4_CONF_OFF)
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#define IA_HPET_T4_COMP (IA_HPET_BASE_ADDR + IA_HPET_T4_COMP_OFF)
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#define IA_HPET_T4_MSI (IA_HPET_BASE_ADDR + IA_HPET_T4_MSI_OFF)
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#define IA_HPET_T5_CONF (IA_HPET_BASE_ADDR + IA_HPET_T5_CONF_OFF)
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#define IA_HPET_T5_COMP (IA_HPET_BASE_ADDR + IA_HPET_T5_COMP_OFF)
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#define IA_HPET_T5_MSI (IA_HPET_BASE_ADDR + IA_HPET_T5_MSI_OFF)
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#define IA_HPET_T6_CONF (IA_HPET_BASE_ADDR + IA_HPET_T6_CONF_OFF)
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#define IA_HPET_T6_COMP (IA_HPET_BASE_ADDR + IA_HPET_T6_COMP_OFF)
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#define IA_HPET_T6_MSI (IA_HPET_BASE_ADDR + IA_HPET_T6_MSI_OFF)
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#define IA_HPET_T7_CONF (IA_HPET_BASE_ADDR + IA_HPET_T7_CONF_OFF)
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#define IA_HPET_T7_COMP (IA_HPET_BASE_ADDR + IA_HPET_T7_COMP_OFF)
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#define IA_HPET_T7_MSI (IA_HPET_BASE_ADDR + IA_HPET_T7_MSI_OFF)
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#else
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IMPORT ULONG vxbIaHpetBaseAddr;
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#define IA_HPET_GEN_CAP (vxbIaHpetBaseAddr + IA_HPET_GEN_CAP_OFF)
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#define IA_HPET_GEN_CON (vxbIaHpetBaseAddr + IA_HPET_GEN_CON_OFF)
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#define IA_HPET_INT_STS (vxbIaHpetBaseAddr + IA_HPET_INT_STS_OFF)
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#define IA_HPET_MN_CNTR (vxbIaHpetBaseAddr + IA_HPET_MN_CNTR_OFF)
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#define IA_HPET_T0_CONF (vxbIaHpetBaseAddr + IA_HPET_T0_CONF_OFF)
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#define IA_HPET_T0_COMP (vxbIaHpetBaseAddr + IA_HPET_T0_COMP_OFF)
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#define IA_HPET_T0_MSI (vxbIaHpetBaseAddr + IA_HPET_T0_MSI_OFF)
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#define IA_HPET_T1_CONF (vxbIaHpetBaseAddr + IA_HPET_T1_CONF_OFF)
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#define IA_HPET_T1_COMP (vxbIaHpetBaseAddr + IA_HPET_T1_COMP_OFF)
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#define IA_HPET_T1_MSI (vxbIaHpetBaseAddr + IA_HPET_T1_MSI_OFF)
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#define IA_HPET_T2_CONF (vxbIaHpetBaseAddr + IA_HPET_T2_CONF_OFF)
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#define IA_HPET_T2_COMP (vxbIaHpetBaseAddr + IA_HPET_T2_COMP_OFF)
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#define IA_HPET_T2_MSI (vxbIaHpetBaseAddr + IA_HPET_T2_MSI_OFF)
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#define IA_HPET_T3_CONF (vxbIaHpetBaseAddr + IA_HPET_T3_CONF_OFF)
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#define IA_HPET_T3_COMP (vxbIaHpetBaseAddr + IA_HPET_T3_COMP_OFF)
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#define IA_HPET_T3_MSI (vxbIaHpetBaseAddr + IA_HPET_T3_MSI_OFF)
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#define IA_HPET_T4_CONF (vxbIaHpetBaseAddr + IA_HPET_T4_CONF_OFF)
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#define IA_HPET_T4_COMP (vxbIaHpetBaseAddr + IA_HPET_T4_COMP_OFF)
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#define IA_HPET_T4_MSI (vxbIaHpetBaseAddr + IA_HPET_T4_MSI_OFF)
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#define IA_HPET_T5_CONF (vxbIaHpetBaseAddr + IA_HPET_T5_CONF_OFF)
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#define IA_HPET_T5_COMP (vxbIaHpetBaseAddr + IA_HPET_T5_COMP_OFF)
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#define IA_HPET_T5_MSI (vxbIaHpetBaseAddr + IA_HPET_T5_MSI_OFF)
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#define IA_HPET_T6_CONF (vxbIaHpetBaseAddr + IA_HPET_T6_CONF_OFF)
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#define IA_HPET_T6_COMP (vxbIaHpetBaseAddr + IA_HPET_T6_COMP_OFF)
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#define IA_HPET_T6_MSI (vxbIaHpetBaseAddr + IA_HPET_T6_MSI_OFF)
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#define IA_HPET_T7_CONF (vxbIaHpetBaseAddr + IA_HPET_T7_CONF_OFF)
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#define IA_HPET_T7_COMP (vxbIaHpetBaseAddr + IA_HPET_T7_COMP_OFF)
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#define IA_HPET_T7_MSI (vxbIaHpetBaseAddr + IA_HPET_T7_MSI_OFF)
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#endif /* !_WRS_CONFIG_LP64 */
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#ifndef _ASMLANGUAGE
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#define IA_HPET_GEN_READ64(addr, value) (value = (*(volatile UINT64 *)addr))
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#define IA_HPET_GEN_WRITE64(addr, value) ((*(volatile UINT64 *)addr) = value)
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#define IA_HPET_GEN_READ32(addr, value) (value = (*(volatile UINT32 *)addr))
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#define IA_HPET_GEN_WRITE32(addr, value) ((*(volatile UINT32 *)addr) = value)
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#define IA_HPET_TIMERn_READ64(base, id, value) (value = *(volatile UINT64 *)\
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(base + id * 0x20))
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#define IA_HPET_TIMERn_WRITE64(base, id, value) (*(volatile UINT64 *)\
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(base + id * 0x20) = value)
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#define IA_HPET_TIMERn_READ32(base, id, value) (value = *(volatile UINT32 *)\
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(base + id * 0x20))
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#define IA_HPET_TIMERn_WRITE32(base, id, value) (*(volatile UINT32 *)\
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(base + id * 0x20) = value)
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LOCAL __inline__ UINT64 iaHpetRead64 (void)
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{
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UINT64 value;
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value = *(volatile UINT64 *)IA_HPET_MN_CNTR;
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#ifndef _WRS_CONFIG_LP64
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if (((*(volatile UINT64 *)IA_HPET_MN_CNTR) & 0x00000000ffffffffULL) <
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(value & 0x00000000ffffffffULL))
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value = *(volatile UINT64 *)IA_HPET_MN_CNTR;
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#endif
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return value;
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}
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/* macros */
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#define IA_HPET_READ32(value) value = *(volatile UINT32 *)IA_HPET_MN_CNTR
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#define IA_HPET_READ64(value) value = iaHpetRead64()
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#undef HPET_DEBUG
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#if defined (HPET_DEBUG)
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IMPORT void earlyPrint (char * outString);
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#endif /* HPET_DEBUG */
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IMPORT BOOL vxbDelayTimerFreeRunning;
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IMPORT STATUS sysMmuMapAdd();
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IMPORT UINT8 *sysInumTbl; /* IRQ vs intNum table */
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IMPORT unsigned int vxCpuLoApicId (void);
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/* prototypes */
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IMPORT void vxbIaHpetTimerDrvRegister (void);
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IMPORT STATUS iaHpetOneShotEnable (VXB_DEVICE_ID pInst,
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UINT32 timerId,
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UINT64 timeoutTs,
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void *pIsr,
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UINT32 arg);
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IMPORT UINT64 iaHpetOneShotDisable (VXB_DEVICE_ID pInst, UINT32 timerId);
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IMPORT UINT64 iaHpetTimerBaseGet (VXB_DEVICE_ID pInst, UINT32 timerId);
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IMPORT UINT64 iaHpetTimerPeriodGet (VXB_DEVICE_ID pInst, UINT32 timerId);
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IMPORT UINT32 iaHpetTimerFreqGet (VXB_DEVICE_ID pInst, UINT32 timerId);
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IMPORT void iaHpetTimerCfgShow (void);
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __INCvxbIaHpetTimerh */
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