152 lines
4.7 KiB
C
152 lines
4.7 KiB
C
/* cacheArmLib.h - ARM cache library header file */
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/*
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* Copyright (c) 1996-2008, 2010-2012, 2014 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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06jan14,c_l Improve cache operation. (VXW6-27040)
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01w,17jul12,j_b Add Cortex-A15 cache support
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01v,07feb12,c_l Fix compiling error. (WIND00294062)
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01u,13jan11,m_h moving cacheArchAlignSize to arm.h
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01t,29apr10,pad Moved extern C statement after include statements.
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01s,02jul07,m_h Adding support for MPCore
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01r,12jun08,j_b add Cortex-A/-R cache support
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01q,22may06,m_h 946 Support
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01p,22feb06,m_h Manzano Support
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01o,28mar05,jb Adding 1136jfs Support
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01n,25jan05,jb Removing in-advertant addition of 1136
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01m,07dec04,jb Restructure for Base6
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01l,01dec03,scm modify for AIM support...
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01k,17dec02,jb Adding ARM10 and 926E support
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01k,24jan03,jb Resolve SPR 81285 and 82533
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01j,02oct01,jpd added definitions to support simplifications in source.
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01i,12nov01,to added cacheArchIntMask (merged from AE)
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01h,23jul01,scm change XScale name to conform to coding standards...
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01g,11dec00,scm replace references to ARMSA2 with XScale
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01f,01sep00,scm add sa2 support...
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01e,07sep99,jpd added ARM920T support.
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01d,24nov98,jpd added ARM940T, ARMSA1100, ARMSA1500 support;
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cdp restructured for multiple cache/MMU libraries.
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01c,09mar98,jpd tidied.
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01b,16sep97,jpd added cacheIMBRange(), 810 definitions for cacheDClear() and
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cacheArchIntLock().
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01a,09may96,cdp created
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*/
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/*
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* N.B. although this library contains code written for the ARM810
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* CPU, at the time of writing, this code has not been fully tested on
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* that CPU. YOU HAVE BEEN WARNED.
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*/
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#ifndef __INCcacheArmLibh
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#define __INCcacheArmLibh
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#ifndef _ASMLANGUAGE
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/*
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* Variable used to hold the interrupt mask used when disabling
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* interrupts for lengthy cache operations such as cache flushing. This
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* is preinitialised to a mask that disables IRQs and FIQs. The BSP may
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* change this. Do not do so unless you are sure that you understand the
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* consequences. In particular, if interrupts are allowed to occur
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* during these operations, the state of the cache afterwards may be
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* indeterminate.
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*/
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IMPORT UINT32 cacheArchIntMask;
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/* routine that locks interrupts according to the mask above */
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IMPORT UINT32 cacheArchIntLock (void);
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#endif /* _ASMLANGUAGE */
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/*
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* Arm Arch HW specific bits used by cache routines...
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*/
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#define CACHE_MM_ENABLE (1<<0) /* MMU enable */
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#define CACHE_DC_ENABLE (1<<2) /* (data) cache enable */
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#define CACHE_WB_ENABLE (1<<3) /* write buffer enable */
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#define CACHE_IC_ENABLE (1<<12) /* Instruction cache enable */
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#define LoC_MASK 0x07000000 /* level of coherency mask of CLIDR */
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#define LoC_SHIFT 23 /* level of coherency shift of CLIDR */
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#define LoUU_MASK 0x38000000 /* level of coherency mask of CLIDR */
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#define LoUU_SHIFT 26 /* level of coherency shift of CLIDR */
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/*
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* Reset Architecture specific cache behavior.
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* It is set with the cpu include file.
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*/
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#undef ARMCACHE_NOT_COHERENT
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#undef ARMCACHE_HAS_WRITETHROUGH
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#undef ARMCACHE_HAS_MINICACHE
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#undef ARMCACHE_NEEDS_IMB
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#if (ARMCACHE == ARMCACHE_926E)
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#include "cacheArm926eLib.h"
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#elif (ARMCACHE == ARMCACHE_946E)
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#include "cacheArm946eLib.h"
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#elif (ARMCACHE == ARMCACHE_920T)
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#include "cacheArm920tLib.h"
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#elif (ARMCACHE == ARMCACHE_940T)
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#include "cacheArm940tLib.h"
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#elif (ARMCACHE == ARMCACHE_1022E)
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#include "cacheArm1022eLib.h"
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#elif (ARMCACHE == ARMCACHE_1136JF)
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#include "cacheArm1136jfLib.h"
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#elif (ARMCACHE == ARMCACHE_XSCALE)
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#include "cacheArmXSCALELib.h"
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#elif (ARMCACHE == ARMCACHE_MANZANO)
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#include "cacheArmManzanoLib.h"
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#elif (ARMCACHE == ARMCACHE_CORTEXA8)
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#include "cacheCortexA8Lib.h"
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#elif (ARMCACHE == ARMCACHE_11MPCORE)
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#include "cacheArm11MPCoreLib.h"
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#elif (ARMCACHE == ARMCACHE_CORTEXA15)
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#include "cacheCortexA15Lib.h"
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#endif /* ARMCACHE == ARMCACHE_926E */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if (ARMCACHE != ARMCACHE_NONE)
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/*
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* Verify the cpu has established some special attributes
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*/
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#ifndef ARMCACHE_NOT_COHERENT
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#error ARMCACHE value not supported in definition of ARMCACHE_NOT_COHERENT
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#endif
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#ifndef ARMCACHE_HAS_WRITETHROUGH
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#error ARMCACHE value not supported in definition of ARMCACHE_HAS_WRITETHROUGH
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#endif
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#ifndef ARMCACHE_HAS_MINICACHE
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#define ARMCACHE_HAS_MINICACHE FALSE
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#endif
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#ifndef ARMCACHE_NEEDS_IMB
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#error ARMCACHE value not supported in definition of ARMCACHE_NEEDS_IMB
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#endif
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#endif /* ARMCACHE_NONE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCcacheArmLibh */
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