447 lines
17 KiB
C
447 lines
17 KiB
C
/* wancomEnd.h - Marvel/Galileo GT642xx network interface header */
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/*
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* Copyright (c) 2002, 2004-2005, 2010 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/* Copyright 2002 Motorola, Inc. All Rights Reserved */
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/*
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modification history
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--------------------
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01f,06may10,c_t change WANCOM_BUF_DEF_SIZE from 1518 to 1520(WIND00204839)
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01e,09feb05,mdo Documentation fixes for apigen
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01d,28jun04,h_k added pNetBufCfg and initType, deleted memBaseState and
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hashState in WANCOM_DRV_CTRL and pMblk in RX_DESC.
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01c,11jun04,h_k changed comment for baseAddr. merged wancomDefs.h.
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01b,26mar04,h_k merged from cp7000g BSP.
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01a,28oct02,scb Copied from hxeb100 base version 01a.
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*/
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/*
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********************************************************************************
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* (c), Copyright 2001, Marvell International Ltd. *
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* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL SEMICONDUCTOR, INC. *
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* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT *
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* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE *
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* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. *
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* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESS, IMPLIED *
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* OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. *
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********************************************************************************
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* wancomEnd.h - Header File for : GT-642xx network interface header
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*
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* DESCRIPTION:
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* This file defines the network devices that can be attached to the MUX.
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*
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* DEPENDENCIES:
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* WRS endLib library.
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*
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********************************************************************************
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*/
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#ifndef __INCwancomEndh
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#define __INCwancomEndh
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/* includes */
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#include "etherLib.h"
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#include "miiLib.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* defines */
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#define DRV_NAME "wancom"
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/* descriptor defines */
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#define SHADOW_OWNER_BY_GT 1
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#define SHADOW_OWNER_BY_CPU 0
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#define OWNER_BY_GT (1<<31)
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#define FIRST (1<<17)
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#define LAST (1<<16)
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#define ENABLE_INTERRUPT (1<<23)
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#define PADDING (1<<18)
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#define GENERATE_CRC (1<<22)
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#define ERROR_SUMMARY (1<<15)
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/* this macros are used to enable access to MPSC_SDCMR */
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#define ENABLE_RX_DMA (1<<7)
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#define ABORT_RECEIVE (1<<15)
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#define STOP_TRANSMIT (1<<16)
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#define PORT_SDMA_STOP_TX_LOW (1<<17)
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#define TX_DEMAND (1<<23)
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#define PORT_SDMA_START_TX_LOW (1<<24)
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#define ABORT_TRANSMIT (1<<31)
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/* Serial second layer cause registers bits definition */
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/* Ethernet mask bits */
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#define RX_BUFFER_RETURN 0x1
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#define TX_BUFFER_HIGH_PRIO 0x4
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#define TX_BUFFER_LOW_PRIO 0x8
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#define TX_END_HIGH_PRIO 0x40
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#define TX_END_LOW_PRIO 0x80
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#define RX_RESOURCE_ERR 0x100
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#define TX_RESOURCE_ERR_HIGH_PRIO 0x400
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#define TX_RESOURCE_ERR_LOW_PRIO 0x800
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#define RX_OVERRUN 0x1000
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#define TX_UNDERRUN 0x2000
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#define RX_BUFFER_QUEUE_0 (1<<16)
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#define RX_BUFFER_QUEUE_1 (1<<17)
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#define RX_BUFFER_QUEUE_2 (1<<18)
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#define RX_BUFFER_QUEUE_3 (1<<19)
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#define RX_ERROR_QUEUE_0 (1<<20)
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#define RX_ERROR_QUEUE_1 (1<<21)
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#define RX_ERROR_QUEUE_2 (1<<22)
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#define RX_ERROR_QUEUE_3 (1<<23)
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#define MII_PHYS_STATUS_CHANGE 0x10000000
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#define SMI_COMMAND_DONE 0x20000000
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#define ETHER_INT_SUM 0x80000000
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/* Serial Port Multiplex register (connect to MII control) */
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#define SERIAL_PORT_MULTIPLEX 0xf010
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#define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400
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#define NIBBLE_SWAPPING_16_BIT(X) (((X&0xf)<<4) | ((X&0xf0)>>4) | \
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((X&0xf00)<<4) | ((X&0xf000)>>4))
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#define NIBBLE_SWAPPING_32_BIT(X) (((X&0xf)<<4) | ((X&0xf0)>>4) | \
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((X&0xf00)<<4) | ((X&0xf000)>>4) | ((X&0xf0000)<<4) | \
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((X&0xf00000)>>4) | ((X&0xf000000)<<4) | ((X&0xf0000000)>>4))
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#define GT_NIBBLE(X) ((X&0x1)<<3)+((X&0x2)<<1)+((X&0x4)>>1)+((X&0x8)>>3)
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#define FLIP_6_BITS(X) (((X&0x1)<<5)+((X&0x2)<<3)+((X&0x4)<<1)+ \
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((X&0x8)>>1)+((X&0x10)>>3)+((X&0x20)>>5))
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#define FLIP_9_BITS(X) (((X&0x1)<<8)+((X&0x2)<<6)+((X&0x4)<<4)+ \
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((X&0x8)<<2)+((X&0x10)<<0)+((X&0x20)>>2)+((X&0x40)>>4)+ \
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((X&0x80)>>6)+((X&0x100)>>8))
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#define _8K_TABLE 0
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/* size of hash entry for an address */
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#define MAC_ENTRY_SIZE 8
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/* hash table entry fields */
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#define VALID_BIT 0
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#define VALID 1
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#define NOT_VALID 0
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#define SKIP_BIT 1
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#define SKIP (1<<1)
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#define DONT_SKIP 0
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#define RD_BIT 2
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#define RCV_PKT 1
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#define DROP_RCV_PKT 0
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#define HOP_NUMBER 12
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#define EIGHT_K 0x8000
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#define HALF_K 0x8000/16
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#define HASH_DEFUALT_MODE 14
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#define HASH_MODE 13
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#define HASH_SIZE 12
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#define PROMISCUOUS_MODE 0
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#define WANCOM_BUF_DEF_SIZE (SIZEOF_ETHERHEADER + ETHERMTU + 4 + 2)
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/* For buffers less than 8 bytes */
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#define TX_BUF_OFFSET_IN_DESC 0x18
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/* ethernet configuration value */
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#define PORT_CONFIG_VALUE 0x00000081
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/* Ethernet config ext. value */
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#define PORT_CONFIG_EXTEND_VALUE 0x00010800
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/* SDMA configure value */
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#if (_BYTE_ORDER == _BIG_ENDIAN)
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/* big endian DMA transfer mode */
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#define PORT_SDMA_CONFIG_VALUE 0x00002000
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#else
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/* little endian DMA transfer mode */
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#define PORT_SDMA_CONFIG_VALUE 0x000020c0
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#endif /* _BYTE_ORDER == _BIG_ENDIAN */
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/* serial ports multiple x reg (RMII and mpsc's connected) */
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#define GT_SERIAL_PORT_MUX 0x00000001
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#ifndef WANCOM_SYS_INT_CONNECT
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#define WANCOM_SYS_INT_CONNECT(pDrvCtrl, pFunc, arg, pRet) \
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{ \
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*pRet = ERROR ; \
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if(wancomEndIntConnect != NULL) \
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{ \
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*pRet = (wancomEndIntConnect) ( \
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INUM_TO_IVEC (pDrvCtrl->port.vector), \
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(VOIDFUNCPTR*)(pFunc), (int) (arg)); \
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} \
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}
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#endif /* WANCOM_SYS_INT_CONNECT */
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#ifndef WANCOM_SYS_INT_DISCONNECT
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#define WANCOM_SYS_INT_DISCONNECT(pDrvCtrl, pFunc, arg, pRet) \
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{ \
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*pRet = ERROR ; \
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if(wancomEndIntDisconnect != NULL) \
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{ \
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*pRet = (wancomEndIntDisconnect) ((VOIDFUNCPTR*) \
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INUM_TO_IVEC (pDrvCtrl->port.level), \
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(pFunc), (int) (arg)); \
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} \
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}
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#endif /* WANCOM_SYS_INT_DISCONNECT */
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#ifndef WANCOM_SYS_INT_ENABLE
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#define WANCOM_SYS_INT_ENABLE(pDrvCtrl) \
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if (WANCOM_INT_ENABLE (pDrvCtrl)) \
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((*(FUNCPTR) (WANCOM_INT_ENABLE (pDrvCtrl))) (pDrvCtrl->unit))
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#endif /* WANCOM_SYS_INT_ENABLE */
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#ifndef WANCOM_SYS_INT_DISABLE
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#define WANCOM_SYS_INT_DISABLE(pDrvCtrl) \
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if (WANCOM_INT_DISABLE (pDrvCtrl)) \
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((*(FUNCPTR) (WANCOM_INT_DISABLE (pDrvCtrl))) (pDrvCtrl->unit))
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#endif /* WANCOM_SYS_INT_DISABLE */
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#ifndef WANCOM_SYS_INT_ACK
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#define WANCOM_SYS_INT_ACK(pDrvCtrl) \
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if (WANCOM_INT_ACK (pDrvCtrl)) \
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((*(FUNCPTR) (WANCOM_INT_ACK (pDrvCtrl))) (pDrvCtrl->unit))
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#endif /* WANCOM_SYS_INT_ACK */
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#ifndef LOCAL_TO_SYS_ADDR
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#define LOCAL_TO_SYS_ADDR(unit,localAddr) \
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((int) pDrvCtrl->port.sysLocalToBus ? \
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(*pDrvCtrl->port.sysLocalToBus) (unit, localAddr) : localAddr)
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#endif /* LOCAL_TO_SYS_ADDR */
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#ifndef SYS_TO_LOCAL_ADDR
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#define SYS_TO_LOCAL_ADDR(unit,sysAddr) \
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((int) pDrvCtrl->port.sysBusToLocal ? \
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(*pDrvCtrl->port.sysBusToLocal)(unit, sysAddr) : sysAddr)
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#endif /* SYS_TO_LOCAL_ADDR */
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/* CPU interface registers */
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#define WANCOM_DEV_NAME "wancom"
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#define WANCOM_DEV_NAME_LEN 7
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#define DEF_NUM_CFDS 32 /* default number of CFDs (Hex) */
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#define DEF_NUM_RFDS 32 /* default number of RFDs (Hex) */
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#define WANCOM_100MBS 100000000 /* bits per sec */
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#define WANCOM_10MBS 10000000 /* bits per sec */
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#define WANCOM_ADDR_LEN 6 /* ethernet address length */
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/* constants needed within this file */
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#define EH_SIZE 14 /* avoid structure padding issues */
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#define N_MCAST 12
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/* offsets from 642xx register base address */
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#define PORT0_BASE_OFFSET 0x2400 /* ethernet 0 base addr */
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#define ETH_SMIR_BASE_OFFSET 0x2010 /* SMIR register */
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#define ETH_PHY_BASE_OFFSET 0x2000 /* Phy register */
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/* Ethernet port register offsets from port base address */
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#define PORT_CONFIG_REG 0x000
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#define PORT_CONFIG_EXTEND_REG 0x008
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#define PORT_COMMAND_REG 0x010
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#define PORT_STATUS_REG 0x018
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#define SERIAL_PARAMETERS_REG 0x020
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#define HASH_TABLE_POINTER_REG 0x028
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#define FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x030
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#define FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x038
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#define SDMA_CONFIGURATION_REG 0x040
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#define SDMA_COMMAND_REG 0x048
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#define INTERRUPT_CAUSE_REG 0x050
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#define INTERRUPT_MASK_REG 0x058
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#define FIRST_RX_DESC_PTR0_OFFSET 0x080
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#define FIRST_RX_DESC_PTR1_OFFSET 0x084
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#define FIRST_RX_DESC_PTR2_OFFSET 0x088
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#define FIRST_RX_DESC_PTR3_OFFSET 0x08c
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#define CURRENT_RX_DESC_PTR0_OFFSET 0x0a0
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#define CURRENT_RX_DESC_PTR1_OFFSET 0x0a4
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#define CURRENT_RX_DESC_PTR2_OFFSET 0x0a8
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#define CURRENT_RX_DESC_PTR3_OFFSET 0x0ac
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#define CURRENT_TX_DESC_PTR0_OFFSET 0x0e0
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#define CURRENT_TX_DESC_PTR1_OFFSET 0x0e4
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#define MIB_COUNTER_BASE 0x100
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#define MIB_COUNTER_END 0x200
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/* Port status register bits offset in register */
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#define SPEED_100MBS (1<<0)
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#define LINK_UP_BIT (1<<3)
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#define TX_LOW_RUNNING (1<<5)
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#define TX_HIGH_RUNNING (1<<6)
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#define TX_IN_PROGRESS (1<<7)
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/* Port Config register bits offset in register */
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#define PROMISCUOUS_MODE_BIT (1<<0)
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/* typedefs */
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/* board specific information */
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typedef struct
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{
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UINT32 vector; /* interrupt vector */
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UINT32 level; /* interrupt level */
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UINT32 baseAddr; /* Port registers base address */
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UCHAR enetAddr[8]; /* eth address with 2 byte pad */
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int (*intEnable)(int unit); /* port interrupt enable routine */
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int (*intDisable)(int unit); /* port interrupt disable routine */
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int (*intAck) (int unit); /* interrupt ack */
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UINT32 portConfig;
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UINT32 portConfigExtend;
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UINT32 portCommand;
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UINT32 portSdmaConfig;
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int offset;
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} WANCOM_PORT_INFO;
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typedef unsigned int RX_COMMAND;
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typedef struct SdmaRxDesc
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{
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#if (_BYTE_ORDER == _BIG_ENDIAN)
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unsigned int bufsize :16;
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volatile unsigned int bytecnt :16;
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volatile RX_COMMAND cmd_sts;
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unsigned int next_desc_ptr;
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volatile unsigned int buf_ptr;
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#else /* _BYTE_ORDER == _BIG_ENDIAN */
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volatile RX_COMMAND cmd_sts;
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volatile unsigned int bytecnt :16;
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unsigned int bufsize :16;
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unsigned int buf_ptr;
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unsigned int next_desc_ptr;
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#endif /* _BYTE_ORDER == _BIG_ENDIAN */
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M_BLK_ID pMblk;
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/* to be safe, align the structure size multiple of 32 bytes */
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unsigned int reserved [3];
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} RX_DESC;
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typedef unsigned int TX_COMMAND;
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/* tx descriptor definition. buf is used for sending small buffers
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* less than 8 bytes in size. buf is placed so it is on a boundary
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* that is divisible by 8 (required for buffers <= 8 bytes) and
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* sized so the descriptor is divisible evenly by 16
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*/
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typedef struct SdmaTxDesc
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{
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#if (_BYTE_ORDER == _BIG_ENDIAN)
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unsigned int bytecnt :16;
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unsigned int shadowOwner :16;
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volatile TX_COMMAND cmd_sts;
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unsigned int next_desc_ptr;
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unsigned int buf_ptr;
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#else /* _BYTE_ORDER == _BIG_ENDIAN */
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volatile TX_COMMAND cmd_sts;
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unsigned int shadowOwner :16;
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unsigned int bytecnt :16;
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unsigned int buf_ptr;
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unsigned int next_desc_ptr;
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#endif /* _BYTE_ORDER == _BIG_ENDIAN */
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UINT8 buf [8];
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M_BLK * pointerToRxQueue;
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char * txBuffPtr;
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} TX_DESC;
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/* The definition of the driver control structure */
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typedef struct wancom_drv_ctrl
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{
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END_OBJ endObj; /* base class */
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int unit; /* unit number */
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char * pMemBase; /* memory pool base */
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ULONG memSize; /* memory pool size */
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char * pClsBase; /* cluster pool base */
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char * pMemArea; /* Mblk Clblk pool pointer */
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char * pTxBuffBase; /* tx buffer base address */
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int nCFDs; /* how many CFDs to create */
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volatile int nFreeCFDs; /* how many CFDs freed */
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int nRFDs; /* how many RFDs to create */
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UINT32 pCSR; /* pointer to CSR base */
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RX_DESC* headRxDescPtr; /* Pointer to head Rx desc queue */
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RX_DESC* rxDescMem; /* Pointer to start of Rx desc memory */
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TX_DESC* usedTxDescPtr; /* Pointer to head Tx desc queue */
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TX_DESC* currTxDescPtr; /* Pointer to next available Tx desc */
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TX_DESC* txDescMem; /* Pointer to start of Tx desc memory */
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UINT16 flags; /* driver state */
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BOOL attached; /* interface has been attached */
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BOOL rxHandle; /* rx handler scheduled */
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BOOL txHandle; /* tx handler scheduled */
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BOOL txStall; /* tx handler stalled - no CFDs */
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END_ERR lastError; /* Last error passed to muxError */
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WANCOM_PORT_INFO port; /* port specific info */
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CL_POOL_ID pClPoolId; /* cluster pool identifier */
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int addressTableHashMode ;
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int addressTableHashSize ;
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UINT32 addressTableBase ;
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char * addressTableMalloc ;
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int initType; /* memory pool initialization type */
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NETBUF_CFG * pNetBufCfg;
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} WANCOM_DRV_CTRL;
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#if (_BYTE_ORDER == _BIG_ENDIAN)
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#define PSWAP(x) LONGSWAP(x)
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#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
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#define PSWAP(x) (x)
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#endif
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#ifndef EIEIO
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#define EIEIO
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#endif
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#define WANCOM_REG_RD(x,val) \
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{ \
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UINT32 tmp ; \
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tmp = *((volatile UINT32*)(x)); \
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EIEIO ; \
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(*val) = PSWAP(tmp); \
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EIEIO ; \
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}
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#define WANCOM_REG_WR(x,val) \
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{ \
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UINT32 tmp ; \
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tmp = PSWAP(val); \
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EIEIO ; \
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*((volatile UINT32*)(x)) = tmp ; \
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EIEIO ; \
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tmp = *((volatile UINT32*)(x)); \
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCwancomEndh */
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