541 lines
25 KiB
C
541 lines
25 KiB
C
/* mcfIntc.h - coldfire programmable interrupt timer device header */
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/*
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* Copyright 2007, 2008 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01b,06feb08,rec change CAST_M5208 macros to more generic type
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01a,14nov07,rec created
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*/
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#ifndef __INCmcfIntch
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#define __INCmcfIntch
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/* Register read/write macros */
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#define MCF_INTC_IPRH_OFF 0x000
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#define MCF_INTC_IPRL_OFF 0x004
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#define MCF_INTC_IMRH_OFF 0x008
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#define MCF_INTC_IMRL_OFF 0x00C
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#define MCF_INTC_INTFRCH_OFF 0x010
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#define MCF_INTC_INTFRCL_OFF 0x014
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#define MCF_INTC_ICONFIG_OFF 0x01A
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#define MCF_INTC_SIMR_OFF 0x01C
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#define MCF_INTC_CIMR_OFF 0x01D
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#define MCF_INTC_CLMASK_OFF 0x01E
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#define MCF_INTC_SLMASK_OFF 0x01F
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#define MCF_INTC_ICR0_OFF 0x040
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#define MCF_INTC_ICR1_OFF 0x041
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#define MCF_INTC_ICR2_OFF 0x042
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#define MCF_INTC_ICR3_OFF 0x043
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#define MCF_INTC_ICR4_OFF 0x044
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#define MCF_INTC_ICR5_OFF 0x045
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#define MCF_INTC_ICR6_OFF 0x046
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#define MCF_INTC_ICR7_OFF 0x047
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#define MCF_INTC_ICR8_OFF 0x048
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#define MCF_INTC_ICR9_OFF 0x049
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#define MCF_INTC_ICR10_OFF 0x04A
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#define MCF_INTC_ICR11_OFF 0x04B
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#define MCF_INTC_ICR12_OFF 0x04C
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#define MCF_INTC_ICR13_OFF 0x04D
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#define MCF_INTC_ICR14_OFF 0x04E
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#define MCF_INTC_ICR15_OFF 0x04F
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#define MCF_INTC_ICR16_OFF 0x050
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#define MCF_INTC_ICR17_OFF 0x051
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#define MCF_INTC_ICR18_OFF 0x052
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#define MCF_INTC_ICR19_OFF 0x053
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#define MCF_INTC_ICR20_OFF 0x054
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#define MCF_INTC_ICR21_OFF 0x055
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#define MCF_INTC_ICR22_OFF 0x056
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#define MCF_INTC_ICR23_OFF 0x057
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#define MCF_INTC_ICR24_OFF 0x058
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#define MCF_INTC_ICR25_OFF 0x059
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#define MCF_INTC_ICR26_OFF 0x05A
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#define MCF_INTC_ICR27_OFF 0x05B
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#define MCF_INTC_ICR28_OFF 0x05C
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#define MCF_INTC_ICR29_OFF 0x05D
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#define MCF_INTC_ICR30_OFF 0x05E
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#define MCF_INTC_ICR31_OFF 0x05F
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#define MCF_INTC_ICR32_OFF 0x060
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#define MCF_INTC_ICR33_OFF 0x061
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#define MCF_INTC_ICR34_OFF 0x062
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#define MCF_INTC_ICR35_OFF 0x063
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#define MCF_INTC_ICR36_OFF 0x064
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#define MCF_INTC_ICR37_OFF 0x065
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#define MCF_INTC_ICR38_OFF 0x066
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#define MCF_INTC_ICR39_OFF 0x067
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#define MCF_INTC_ICR40_OFF 0x068
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#define MCF_INTC_ICR41_OFF 0x069
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#define MCF_INTC_ICR42_OFF 0x06A
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#define MCF_INTC_ICR43_OFF 0x06B
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#define MCF_INTC_ICR44_OFF 0x06C
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#define MCF_INTC_ICR45_OFF 0x06D
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#define MCF_INTC_ICR46_OFF 0x06E
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#define MCF_INTC_ICR47_OFF 0x06F
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#define MCF_INTC_ICR48_OFF 0x070
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#define MCF_INTC_ICR49_OFF 0x071
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#define MCF_INTC_ICR50_OFF 0x072
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#define MCF_INTC_ICR51_OFF 0x073
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#define MCF_INTC_ICR52_OFF 0x074
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#define MCF_INTC_ICR53_OFF 0x075
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#define MCF_INTC_ICR54_OFF 0x076
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#define MCF_INTC_ICR55_OFF 0x077
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#define MCF_INTC_ICR56_OFF 0x078
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#define MCF_INTC_ICR57_OFF 0x079
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#define MCF_INTC_ICR58_OFF 0x07A
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#define MCF_INTC_ICR59_OFF 0x07B
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#define MCF_INTC_ICR60_OFF 0x07C
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#define MCF_INTC_ICR61_OFF 0x07D
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#define MCF_INTC_ICR62_OFF 0x07E
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#define MCF_INTC_ICR63_OFF 0x07F
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#define MCF_INTC_SWIACK_OFF 0x0E0
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#define MCF_INTC_L1IACK_OFF 0x0E4
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#define MCF_INTC_L2IACK_OFF 0x0E8
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#define MCF_INTC_L3IACK_OFF 0x0EC
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#define MCF_INTC_L4IACK_OFF 0x0F0
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#define MCF_INTC_L5IACK_OFF 0x0F4
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#define MCF_INTC_L6IACK_OFF 0x0F8
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#define MCF_INTC_L7IACK_OFF 0x0FC
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#define MCF_INTC_IPRH (CAST_MCF_VOL(UINT32)(MCF_INTC_BASE + \
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MCF_INTC_IPRH_OFF))
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#define MCF_INTC_IPRL (CAST_MCF_VOL(UINT32)(MCF_INTC_BASE + \
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MCF_INTC_IPRL_OFF))
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#define MCF_INTC_IMRH (CAST_MCF_VOL(UINT32)(MCF_INTC_BASE + \
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MCF_INTC_IMRH_OFF))
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#define MCF_INTC_IMRL (CAST_MCF_VOL(UINT32)(MCF_INTC_BASE + \
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MCF_INTC_IMRL_OFF))
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#define MCF_INTC_INTFRCH (CAST_MCF_VOL(UINT32)(MCF_INTC_BASE + \
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MCF_INTC_INTFRCH_OFF))
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#define MCF_INTC_INTFRCL (CAST_MCF_VOL(UINT32)(MCF_INTC_BASE + \
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MCF_INTC_INTFRCL_OFF))
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#define MCF_INTC_ICONFIG (CAST_MCF_VOL(UINT16))(MCF_INTC_BASE + \
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MCF_INTC_ICONFIG_OFF))
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#define MCF_INTC_SIMR (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_SIMR_OFF))
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#define MCF_INTC_CIMR (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_CIMR_OFF))
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#define MCF_INTC_CLMASK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_CLMASK_OFF))
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#define MCF_INTC_SLMASK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_SLMASK_OFF))
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#define MCF_INTC_ICR0 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR0_OFF))
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#define MCF_INTC_ICR1 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR1_OFF))
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#define MCF_INTC_ICR2 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR2_OFF))
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#define MCF_INTC_ICR3 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR3_OFF))
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#define MCF_INTC_ICR4 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR4_OFF))
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#define MCF_INTC_ICR5 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR5_OFF))
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#define MCF_INTC_ICR6 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR6_OFF))
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#define MCF_INTC_ICR7 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR7_OFF))
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#define MCF_INTC_ICR8 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR8_OFF))
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#define MCF_INTC_ICR9 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR9_OFF))
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#define MCF_INTC_ICR10 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR10_OFF))
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#define MCF_INTC_ICR11 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR11_OFF))
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#define MCF_INTC_ICR12 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR12_OFF))
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#define MCF_INTC_ICR13 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR13_OFF))
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#define MCF_INTC_ICR14 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR14_OFF))
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#define MCF_INTC_ICR15 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR15_OFF))
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#define MCF_INTC_ICR16 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR16_OFF))
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#define MCF_INTC_ICR17 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR17_OFF))
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#define MCF_INTC_ICR18 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR18_OFF))
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#define MCF_INTC_ICR19 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR19_OFF))
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#define MCF_INTC_ICR20 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR20_OFF))
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#define MCF_INTC_ICR21 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR21_OFF))
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#define MCF_INTC_ICR22 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR22_OFF))
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#define MCF_INTC_ICR23 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR23_OFF))
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#define MCF_INTC_ICR24 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR24_OFF))
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#define MCF_INTC_ICR25 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR25_OFF))
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#define MCF_INTC_ICR26 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR26_OFF))
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#define MCF_INTC_ICR27 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR27_OFF))
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#define MCF_INTC_ICR28 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR28_OFF))
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#define MCF_INTC_ICR29 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR29_OFF))
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#define MCF_INTC_ICR30 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR30_OFF))
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#define MCF_INTC_ICR31 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR31_OFF))
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#define MCF_INTC_ICR32 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR32_OFF))
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#define MCF_INTC_ICR33 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR33_OFF))
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#define MCF_INTC_ICR34 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR34_OFF))
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#define MCF_INTC_ICR35 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR35_OFF))
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#define MCF_INTC_ICR36 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR36_OFF))
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#define MCF_INTC_ICR37 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR37_OFF))
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#define MCF_INTC_ICR38 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR38_OFF))
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#define MCF_INTC_ICR39 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR39_OFF))
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#define MCF_INTC_ICR40 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR40_OFF))
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#define MCF_INTC_ICR41 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR41_OFF))
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#define MCF_INTC_ICR42 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR42_OFF))
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#define MCF_INTC_ICR43 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR43_OFF))
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#define MCF_INTC_ICR44 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR44_OFF))
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#define MCF_INTC_ICR45 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR45_OFF))
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#define MCF_INTC_ICR46 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR46_OFF))
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#define MCF_INTC_ICR47 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR47_OFF))
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#define MCF_INTC_ICR48 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR48_OFF))
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#define MCF_INTC_ICR49 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR49_OFF))
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#define MCF_INTC_ICR50 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR50_OFF))
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#define MCF_INTC_ICR51 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR51_OFF))
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#define MCF_INTC_ICR52 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR52_OFF))
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#define MCF_INTC_ICR53 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR53_OFF))
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#define MCF_INTC_ICR54 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR54_OFF))
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#define MCF_INTC_ICR55 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR55_OFF))
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#define MCF_INTC_ICR56 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR56_OFF))
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#define MCF_INTC_ICR57 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR57_OFF))
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#define MCF_INTC_ICR58 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR58_OFF))
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#define MCF_INTC_ICR59 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR59_OFF))
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#define MCF_INTC_ICR60 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR60_OFF))
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#define MCF_INTC_ICR61 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR61_OFF))
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#define MCF_INTC_ICR62 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR62_OFF))
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#define MCF_INTC_ICR63 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR63_OFF))
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#define MCF_INTC_ICR(x) (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR0_OFF+((x)*0x001)))
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#define MCF_INTC_SWIACK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_SWIACK_OFF))
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#define MCF_INTC_L1IACK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_L1IACK_OFF))
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#define MCF_INTC_L2IACK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_L2IACK_OFF))
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#define MCF_INTC_L3IACK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_L3IACK_OFF))
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#define MCF_INTC_L4IACK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_L4IACK_OFF))
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#define MCF_INTC_L5IACK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_L5IACK_OFF))
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#define MCF_INTC_L6IACK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_L6IACK_OFF))
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#define MCF_INTC_L7IACK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_L7IACK_OFF))
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#define MCF_INTC_LIACK(x) (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_L1IACK_OFF+((x-1)*0x004)))
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/*
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*
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* Interrupt Controller (INTC_IACK)
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*
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*/
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/* Register read/write macros */
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#define MCF_INTC_IACK_GSWIACK (CAST_MCF_VOL(UINT8)(0xFC0540E0))
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#define MCF_INTC_IACK_GL1IACK (CAST_MCF_VOL(UINT8)(0xFC0540E4))
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#define MCF_INTC_IACK_GL2IACK (CAST_MCF_VOL(UINT8)(0xFC0540E8))
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#define MCF_INTC_IACK_GL3IACK (CAST_MCF_VOL(UINT8)(0xFC0540EC))
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#define MCF_INTC_IACK_GL4IACK (CAST_MCF_VOL(UINT8)(0xFC0540F0))
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#define MCF_INTC_IACK_GL5IACK (CAST_MCF_VOL(UINT8)(0xFC0540F4))
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#define MCF_INTC_IACK_GL6IACK (CAST_MCF_VOL(UINT8)(0xFC0540F8))
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#define MCF_INTC_IACK_GL7IACK (CAST_MCF_VOL(UINT8)(0xFC0540FC))
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#define MCF_INTC_IACK_GLIACK(x) (CAST_MCF_VOL(UINT8)(0xFC0540E4+ \
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((x-1)*0x004)))
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/* Bit definitions and macros for MCF_INTC_IACK_GSWIACK */
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#define MCF_INTC_IACK_GSWIACK_VECTOR(x) (((x)&0xFF)<<0)
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/* Bit definitions and macros for MCF_INTC_IACK_GLIACK */
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#define MCF_INTC_IACK_GLIACK_VECTOR(x) (((x)&0xFF)<<0)
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/* Bit definitions and macros for MCF_INTC_IPRH */
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#define MCF_INTC_IPRH_INT32 (0x00000001)
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#define MCF_INTC_IPRH_INT33 (0x00000002)
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#define MCF_INTC_IPRH_INT34 (0x00000004)
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#define MCF_INTC_IPRH_INT35 (0x00000008)
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#define MCF_INTC_IPRH_INT36 (0x00000010)
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#define MCF_INTC_IPRH_INT37 (0x00000020)
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#define MCF_INTC_IPRH_INT38 (0x00000040)
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#define MCF_INTC_IPRH_INT39 (0x00000080)
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#define MCF_INTC_IPRH_INT40 (0x00000100)
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#define MCF_INTC_IPRH_INT41 (0x00000200)
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#define MCF_INTC_IPRH_INT42 (0x00000400)
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#define MCF_INTC_IPRH_INT43 (0x00000800)
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#define MCF_INTC_IPRH_INT44 (0x00001000)
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#define MCF_INTC_IPRH_INT45 (0x00002000)
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#define MCF_INTC_IPRH_INT46 (0x00004000)
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#define MCF_INTC_IPRH_INT47 (0x00008000)
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#define MCF_INTC_IPRH_INT48 (0x00010000)
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#define MCF_INTC_IPRH_INT49 (0x00020000)
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#define MCF_INTC_IPRH_INT50 (0x00040000)
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#define MCF_INTC_IPRH_INT51 (0x00080000)
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#define MCF_INTC_IPRH_INT52 (0x00100000)
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#define MCF_INTC_IPRH_INT53 (0x00200000)
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#define MCF_INTC_IPRH_INT54 (0x00400000)
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#define MCF_INTC_IPRH_INT55 (0x00800000)
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#define MCF_INTC_IPRH_INT56 (0x01000000)
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#define MCF_INTC_IPRH_INT57 (0x02000000)
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#define MCF_INTC_IPRH_INT58 (0x04000000)
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#define MCF_INTC_IPRH_INT59 (0x08000000)
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#define MCF_INTC_IPRH_INT60 (0x10000000)
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#define MCF_INTC_IPRH_INT61 (0x20000000)
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#define MCF_INTC_IPRH_INT62 (0x40000000)
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#define MCF_INTC_IPRH_INT63 (0x80000000)
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/* Bit definitions and macros for MCF_INTC_IPRL */
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#define MCF_INTC_IPRL_INT0 (0x00000001)
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#define MCF_INTC_IPRL_INT1 (0x00000002)
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#define MCF_INTC_IPRL_INT2 (0x00000004)
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#define MCF_INTC_IPRL_INT3 (0x00000008)
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#define MCF_INTC_IPRL_INT4 (0x00000010)
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#define MCF_INTC_IPRL_INT5 (0x00000020)
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#define MCF_INTC_IPRL_INT6 (0x00000040)
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#define MCF_INTC_IPRL_INT7 (0x00000080)
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#define MCF_INTC_IPRL_INT8 (0x00000100)
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#define MCF_INTC_IPRL_INT9 (0x00000200)
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#define MCF_INTC_IPRL_INT10 (0x00000400)
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#define MCF_INTC_IPRL_INT11 (0x00000800)
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#define MCF_INTC_IPRL_INT12 (0x00001000)
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#define MCF_INTC_IPRL_INT13 (0x00002000)
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#define MCF_INTC_IPRL_INT14 (0x00004000)
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#define MCF_INTC_IPRL_INT15 (0x00008000)
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#define MCF_INTC_IPRL_INT16 (0x00010000)
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#define MCF_INTC_IPRL_INT17 (0x00020000)
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#define MCF_INTC_IPRL_INT18 (0x00040000)
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#define MCF_INTC_IPRL_INT19 (0x00080000)
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#define MCF_INTC_IPRL_INT20 (0x00100000)
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#define MCF_INTC_IPRL_INT21 (0x00200000)
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#define MCF_INTC_IPRL_INT22 (0x00400000)
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#define MCF_INTC_IPRL_INT23 (0x00800000)
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#define MCF_INTC_IPRL_INT24 (0x01000000)
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#define MCF_INTC_IPRL_INT25 (0x02000000)
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#define MCF_INTC_IPRL_INT26 (0x04000000)
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#define MCF_INTC_IPRL_INT27 (0x08000000)
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#define MCF_INTC_IPRL_INT28 (0x10000000)
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#define MCF_INTC_IPRL_INT29 (0x20000000)
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#define MCF_INTC_IPRL_INT30 (0x40000000)
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#define MCF_INTC_IPRL_INT31 (0x80000000)
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/* Bit definitions and macros for MCF_INTC_IMRH */
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#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
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#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
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#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
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#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
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#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
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#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
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#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
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#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
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#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
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#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
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#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
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#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
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#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
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#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
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#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
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#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
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#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
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#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
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#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
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#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
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#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
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#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
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#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
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#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
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#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
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#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
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#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
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#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
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#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
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#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
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#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
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#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
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/* Bit definitions and macros for MCF_INTC_IMRL */
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#define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
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#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
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#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
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#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
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#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
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#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
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#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
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#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
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#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
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#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
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#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
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#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
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#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
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#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
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#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
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#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
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#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
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#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
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#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
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#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
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#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
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#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
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#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
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#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
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#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
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#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
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#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
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#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
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#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
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#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
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#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
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#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
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/* Bit definitions and macros for MCF_INTC_INTFRCH */
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#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
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#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
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#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
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#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
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#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
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#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
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#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
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#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
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#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
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#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
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#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
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#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
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#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
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#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
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#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
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#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
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#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
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#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
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#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
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#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
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#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
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#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
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#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
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#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
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#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
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#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
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#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
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#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
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#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
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#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
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#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
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#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
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/* Bit definitions and macros for MCF_INTC_INTFRCL */
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#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001)
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#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
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#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
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#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
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#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
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#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
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#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
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#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
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#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
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#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
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#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
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#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
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#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
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#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
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#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
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#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
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#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
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#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
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#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
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#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
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#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
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#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
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#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
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#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
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#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
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#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
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#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
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#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
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#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
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#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
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#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
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#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
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/* Bit definitions and macros for MCF_INTC_ICONFIG */
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#define MCF_INTC_ICONFIG_EMASK (0x0020)
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#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200)
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#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400)
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#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800)
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#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000)
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#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000)
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#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000)
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#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000)
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/* Bit definitions and macros for MCF_INTC_SIMR */
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#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)<<0)
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/* Bit definitions and macros for MCF_INTC_CIMR */
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#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)<<0)
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/* Bit definitions and macros for MCF_INTC_CLMASK */
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#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)<<0)
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/* Bit definitions and macros for MCF_INTC_SLMASK */
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#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)<<0)
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/* Bit definitions and macros for MCF_INTC_ICR */
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#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<0)
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/* Bit definitions and macros for MCF_INTC_SWIACK */
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#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
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/* Bit definitions and macros for MCF_INTC_LIACK */
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#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
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#endif
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