374 lines
13 KiB
C
374 lines
13 KiB
C
/* cacheLib.h - cache library header file */
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/*
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* Copyright (c) 1990-1998, 2000-2001, 2003-2004, 2007, 2009-2010
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* Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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03v,27oct10,scm WIND00238295 Macro CACHE_DRV_PHYS_TO_VIRT and API cacheDrvPhysToVirt()
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must be removed from VxWorks 64-bit
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03u,27may10,pad Moved extern C statement after include statements.
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03t,07apr10,jpb Added function declarations.
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03s,09dec09,h_k changed cacheDma32Malloc and cacheDma32Free aliases from
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macros in ILP32. fixed the return value for cacheDma32Free().
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03r,29oct09,h_k fixed cacheDma32Malloc and Free macros for ILP32.
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03q,06nov09,pcs Resolve build issue with macro CACHE_TEXT_UPDATE on UP.
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03p,22jun09,x_s use _WRS_CONFIG_SMP VSB option to update CACHE_TEXT_UPDATE
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03o,16sep09,h_k added cacheDma32Malloc and cacheDma32Free.
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03n,19jun09,mze replacing PAD64
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03m,05may09,h_k replaced FUNCPTR with fully qualified function pointer
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parameters.
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03l,20jan09,jb Adding 64-bit support
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03k,13jul07,sru update CACHE_TEXT_UPDATE for SMP
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03j,11jan07,scm rename S_cacheLib_FUNCTION_UNSUPPORTED... to
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S_cacheLib_UNSUPPORTED.
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03i,10jan07,scm add S_cacheLib_FUNCTION_UNSUPPORTED...
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03h,05may04,sru add cacheForeign* API; remove non-ANSI prototypes.
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03g,09may03,pes Move definition of numeric values for cache types out of
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#ifndef _ASMLANGUAGE.
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03f,29apr03,pes PAL conditional compilation cleanup.
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03e,22oct01,dee merge from T2.1.0 coldfire release
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03d,10sep00,hk extended CACHE_TYPE for SH7729.
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03c,01mar00,frf Add SH4 support for T2
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03b,23apr97,hk added SH support.
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03c,05nov98.jpd removed cacheArchLibInit definition for ARM.
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03b,28nov96,cdp added ARM support.
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03a,26may94,yao added PPC support.
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02p,19mar95,dvs removed #ifdef TRON - tron no longer supported.
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02o,08jun94,tpr added branch cache used by MC68060 cpu.
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02n,02dec93,pme Added Am29K family support.
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02m,09jun93,hdn added support for I80X86
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02l,19oct92,jcf reordered xxLibInit params. made CACHE_TYPE v5.0 compatible.
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02k,29sep92,jwt merged cacheLibInit(), cacheReset(), and cacheModeSet().
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02j,22sep92,rrr added support for c++
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02i,20aug92,wmd added #include for i960.
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02h,13aug92,rdc removed instances of cacheLib functions and CACHE_FUNCS
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structures and conditional compilation of corresponding
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IMPORTS.
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02g,30jul92,dnw added cacheLib functions and CACHE_FUNCS structures.
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02f,15jul92,jwt added more CACHE_MODEs.
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02e,09jul92,jwt added virtual-to-physical and physical-to-virtual stuff.
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02d,07jul92,ajm added support for mips
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02c,06jul92,jwt cleaned up cacheDrvXxx() macros by stressing pointers.
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02b,04jul92,jcf cleaned up.
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02a,03jul92,jwt cache library header for 5.1; moved '040 stuff to arch/mc68k.
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01k,16jun92,jwt made safe for assembly language files.
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01j,26may92,rrr the tree shuffle
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-changed includes to have absolute path from h/
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01i,20jan92,shl added cache68kLib.h.
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01h,09jan92,jwt created cacheSPARCLib.h;
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cleaned up ANSI compiler warning messages.
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01g,04oct91,rrr passed through the ansification filter
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-fixed #else and #endif
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-changed copyright notice
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01f,27aug91,shl added scope type for MC68040 caches.
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01e,19jul91,gae renamed architecture specific include file to be xx<arch>.h.
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01d,23jan91,jwt added SPARC cache commands.
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01c,01mar91,hdn added TRON related stuff.
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01b,05oct90,shl added copyright notice; made #endif ANSI style.
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01a,15jul90,jcf written.
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*/
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#ifndef __INCcacheLibh
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#define __INCcacheLibh
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#include <vxWorks.h>
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#include <vwModNum.h>
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#include <limits.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Cache mode soft bit masks */
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#define CACHE_DISABLED 0x00 /* No cache or disabled */
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#define CACHE_WRITETHROUGH 0x01 /* Write-through Mode */
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#define CACHE_COPYBACK 0x02 /* Copyback Mode */
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#define CACHE_WRITEALLOCATE 0x04 /* Write Allocate Mode */
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#define CACHE_NO_WRITEALLOCATE 0x08
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#define CACHE_SNOOP_ENABLE 0x10 /* Bus Snooping */
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#define CACHE_SNOOP_DISABLE 0x20
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#define CACHE_BURST_ENABLE 0x40 /* Cache Burst Cycles */
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#define CACHE_BURST_DISABLE 0x80
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/* Errno values */
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#define S_cacheLib_INVALID_CACHE (M_cacheLib | 1)
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#define S_cacheLib_UNSUPPORTED (M_cacheLib | 2)
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#ifdef _WRS_CONFIG_LP64
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#define S_cacheLib_DMA32_RAM_UNSUPPORTED (M_cacheLib | 3)
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#endif /* _WRS_CONFIG_LP64 */
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/* Value for "entire cache" in length arguments */
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#define ENTIRE_CACHE ULONG_MAX
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/* explicit names of the cache types */
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#define _INSTRUCTION_CACHE 0 /* Instruction Cache(s) */
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#define _DATA_CACHE 1 /* Data Cache(s) */
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#define _BRANCH_CACHE 2 /* Branch Cache(s) */
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#ifndef _ASMLANGUAGE
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#if !defined (_WRS_CACHE_TYPE)
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typedef enum /* CACHE_TYPE */
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{
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INSTRUCTION_CACHE = _INSTRUCTION_CACHE,
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DATA_CACHE = _DATA_CACHE
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} CACHE_TYPE;
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#endif /* _WRS_CACHE_TYPE */
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typedef UINT CACHE_MODE; /* CACHE_MODE */
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typedef STATUS (*CACHEFOREIGNFUNC)(CACHE_TYPE, VIRT_ADDR,
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PHYS_ADDR, size_t);
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typedef struct /* Cache Routine Pointers */
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{
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STATUS (*enableRtn)(CACHE_TYPE); /* cacheEnable() */
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STATUS (*disableRtn)(CACHE_TYPE); /* cacheDisable() */
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STATUS (*lockRtn)(CACHE_TYPE, void *, size_t); /* cacheLock() */
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STATUS (*unlockRtn)(CACHE_TYPE, void *, size_t); /* cacheUnlock() */
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STATUS (*flushRtn)(CACHE_TYPE, void *, size_t); /* cacheFlush() */
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STATUS (*invalidateRtn)(CACHE_TYPE, void *, size_t);/* cacheInvalidate() */
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STATUS (*clearRtn)(CACHE_TYPE, void *, size_t); /* cacheClear() */
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STATUS (*textUpdateRtn)(void *, size_t); /* cacheTextUpdate() */
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STATUS (*pipeFlushRtn)(void); /* cachePipeFlush() */
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void * (*dmaMallocRtn)(size_t); /* cacheDmaMalloc() */
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STATUS (*dmaFreeRtn)(void *); /* cacheDmaFree() */
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void * (*dmaVirtToPhysRtn)(void *);
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/* virtual-to-Physical Translation */
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void * (*dmaPhysToVirtRtn)(void *);
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/* physical-to-Virtual Translation */
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/* explicit prototypes required due to PHYS_ADDR datatype */
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CACHEFOREIGNFUNC foreignFlushRtn; /* cacheForeignFlush() */
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CACHEFOREIGNFUNC foreignInvalidateRtn; /* cacheForeignInvalidate() */
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CACHEFOREIGNFUNC foreignClearRtn; /* cacheForeignClear() */
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} CACHE_LIB;
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/* Cache flush and invalidate support for general use and drivers */
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typedef struct /* Driver Cache Routine Pointers */
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{
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STATUS (*flushRtn)(CACHE_TYPE, void *, size_t); /* cacheFlush() */
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STATUS (*invalidateRtn)(CACHE_TYPE, void *, size_t);/* cacheInvalidate() */
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void * (*virtToPhysRtn)(void *); /* Virtual-to-Physical Translation */
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void * (*physToVirtRtn)(void *); /* Physical-to-Virtual Translation */
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} CACHE_FUNCS;
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/* Cache macros */
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/*
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* SMP requires cacheTextUpdate functionality to be enabled so we can
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* call the function directly. But this functionality is not required
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* for all configurations of UP so we only call it if the textUpdate routine
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* has been initialized.
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*/
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#ifdef _WRS_CONFIG_SMP
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#define CACHE_TEXT_UPDATE(adrs, bytes) \
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cacheTextUpdate ((void *) (adrs), (size_t) (bytes))
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#define CACHE_TEXT_LOCAL_UPDATE(adrs, bytes) \
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cacheTextLocalUpdate ((void *) (adrs), (size_t) (bytes))
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#else
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#define CACHE_TEXT_UPDATE(adrs, bytes) \
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((cacheLib.textUpdateRtn == NULL) ? OK : \
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(cacheLib.textUpdateRtn) ((void *) (adrs), (size_t) (bytes)))
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#define CACHE_TEXT_LOCAL_UPDATE(adrs, bytes) \
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CACHE_TEXT_UPDATE(adrs, (size_t) bytes)
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#endif /* _WRS_CONFIG_SMP */
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#define CACHE_PIPE_FLUSH() \
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((cacheLib.pipeFlushRtn == NULL) ? OK : \
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(cacheLib.pipeFlushRtn) ())
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#define CACHE_DRV_FLUSH(pFuncs, adrs, bytes) \
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(((pFuncs)->flushRtn == NULL) ? OK : \
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((pFuncs)->flushRtn) (DATA_CACHE, (void *) (adrs), (size_t) (bytes)))
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#define CACHE_DRV_INVALIDATE(pFuncs, adrs, bytes) \
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(((pFuncs)->invalidateRtn == NULL) ? OK : \
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((pFuncs)->invalidateRtn) (DATA_CACHE, \
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(void *) (adrs), (size_t) (bytes)))
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#define CACHE_DRV_VIRT_TO_PHYS(pFuncs, adrs) \
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(((pFuncs)->virtToPhysRtn == NULL) ? (void *) (adrs) : \
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(((pFuncs)->virtToPhysRtn) ((void *) (adrs))))
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#ifndef _WRS_CONFIG_LP64
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#define CACHE_DRV_PHYS_TO_VIRT(pFuncs, adrs) \
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(((pFuncs)->physToVirtRtn == NULL) ? (void *) (adrs) : \
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(((pFuncs)->physToVirtRtn) ((void *) (adrs))))
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#endif /* !_WRS_CONFIG_LP64 */
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#define CACHE_DRV_IS_WRITE_COHERENT(pFuncs) \
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((pFuncs)->flushRtn == NULL)
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#define CACHE_DRV_IS_READ_COHERENT(pFuncs) \
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((pFuncs)->invalidateRtn == NULL)
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#define CACHE_DMA_FLUSH(adrs, bytes) \
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CACHE_DRV_FLUSH (&cacheDmaFuncs, (adrs), (bytes))
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#define CACHE_DMA_INVALIDATE(adrs, bytes) \
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CACHE_DRV_INVALIDATE (&cacheDmaFuncs, (adrs), (bytes))
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#define CACHE_DMA_VIRT_TO_PHYS(adrs) \
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CACHE_DRV_VIRT_TO_PHYS (&cacheDmaFuncs, (adrs))
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#ifndef _WRS_CONFIG_LP64
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#define CACHE_DMA_PHYS_TO_VIRT(adrs) \
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CACHE_DRV_PHYS_TO_VIRT (&cacheDmaFuncs, (adrs))
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#endif /* !_WRS_CONFIG_LP64 */
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#define CACHE_DMA_IS_WRITE_COHERENT() \
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CACHE_DRV_IS_WRITE_COHERENT (&cacheDmaFuncs)
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#define CACHE_DMA_IS_READ_COHERENT() \
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CACHE_DRV_IS_READ_COHERENT (&cacheDmaFuncs)
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#define CACHE_USER_FLUSH(adrs, bytes) \
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CACHE_DRV_FLUSH (&cacheUserFuncs, (adrs), (bytes))
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#define CACHE_USER_INVALIDATE(adrs, bytes) \
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CACHE_DRV_INVALIDATE (&cacheUserFuncs, (adrs), (bytes))
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#define CACHE_USER_IS_WRITE_COHERENT() \
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CACHE_DRV_IS_WRITE_COHERENT (&cacheUserFuncs)
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#define CACHE_USER_IS_READ_COHERENT() \
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CACHE_DRV_IS_READ_COHERENT (&cacheUserFuncs)
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/* variable declarations */
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IMPORT CACHE_LIB cacheLib;
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IMPORT CACHE_FUNCS cacheNullFuncs; /* functions for non-cached memory */
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IMPORT CACHE_FUNCS cacheDmaFuncs; /* functions for dma memory */
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IMPORT CACHE_FUNCS cacheUserFuncs; /* functions for user memory */
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IMPORT void * (*cacheDmaMallocRtn)(size_t);
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IMPORT STATUS (*cacheDmaFreeRtn)(void *);
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IMPORT CACHE_MODE cacheDataMode; /* data cache modes for funcptrs */
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IMPORT BOOL cacheDataEnabled;
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IMPORT BOOL cacheMmuAvailable;
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/* function declarations */
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extern STATUS cacheLibInit (CACHE_MODE inst, CACHE_MODE data);
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#if (CPU_FAMILY != ARM)
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extern STATUS cacheArchLibInit (CACHE_MODE inst, CACHE_MODE data);
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#endif
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extern STATUS cacheEnable (CACHE_TYPE cache);
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extern STATUS cacheDisable (CACHE_TYPE cache);
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extern STATUS cacheLock (CACHE_TYPE cache, void * adrs, size_t bytes);
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extern STATUS cacheUnlock (CACHE_TYPE cache, void * adrs, size_t bytes);
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extern STATUS cacheFlush (CACHE_TYPE cache, void * adrs, size_t bytes);
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extern STATUS cacheInvalidate (CACHE_TYPE cache, void *adrs, size_t bytes);
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extern STATUS cacheClear (CACHE_TYPE cache, void * adrs, size_t bytes);
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extern STATUS cacheTextUpdate (void * adrs, size_t bytes);
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extern STATUS cacheTextLocalUpdate (void * adrs, size_t bytes);
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extern STATUS cachePipeFlush (void);
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extern STATUS cacheDmaPoolAlloc (UINT32 initialPageCount, UINT32 pageIncrement);
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extern void * cacheDmaMalloc (size_t bytes);
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extern STATUS cacheDmaFree (void * pBuf);
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extern STATUS cacheDma32PartInit (void);
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extern void * cacheDma32Malloc (size_t nBytes);
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extern STATUS cacheDma32Free (void * pBfr);
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extern STATUS cacheDrvFlush (CACHE_FUNCS * pFuncs, void * adrs, size_t bytes);
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extern STATUS cacheDrvInvalidate (CACHE_FUNCS * pFuncs, void * adrs,
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size_t bytes);
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extern void * cacheDrvVirtToPhys (CACHE_FUNCS * pFuncs, void * adrs);
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#ifndef _WRS_CONFIG_LP64
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extern void * cacheDrvPhysToVirt (CACHE_FUNCS * pFuncs, void * adrs);
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#endif /* !_WRS_CONFIG_LP64 */
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extern STATUS cacheForeignFlush (CACHE_TYPE cache, VIRT_ADDR virtAdrs,
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PHYS_ADDR physAdrs, size_t bytes);
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extern STATUS cacheForeignInvalidate (CACHE_TYPE cache, VIRT_ADDR virtAdrs,
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PHYS_ADDR physAdrs, size_t bytes);
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extern STATUS cacheForeignClear (CACHE_TYPE cache, VIRT_ADDR virtAdrs,
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PHYS_ADDR physAdrs , size_t bytes);
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extern void cacheFuncsSet (void);
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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/*
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* Architecture-specific cache headers.
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*
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* Note: those need the CACHE_TYPE type defined further above.
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*/
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#if (CPU_FAMILY == MC680X0)
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#include "arch/mc68k/cacheMc68kLib.h"
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#endif /* (CPU_FAMILY == MC680X0) */
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#if (CPU_FAMILY == COLDFIRE)
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#include "arch/coldfire/cacheColdfireLib.h"
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#endif /* (CPU_FAMILY == COLDFIRE) */
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#if (CPU_FAMILY == SPARC)
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#include "arch/sparc/cacheSparcLib.h"
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#endif
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#if (CPU_FAMILY == MIPS)
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#include "arch/mips/cacheMipsLib.h"
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#endif /* (CPU_FAMILY == MIPS) */
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#if (CPU_FAMILY == PPC)
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#include "arch/ppc/cachePpcLib.h"
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#endif /* CPU_FAMILY == PPC */
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#if (CPU_FAMILY == I960)
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#include "arch/i960/vxI960Lib.h"
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#endif /* CPU_FAMILY == I960 */
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#if (CPU_FAMILY == I80X86)
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#ifndef _WRS_CONFIG_LP64
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#include "arch/i86/cacheI86Lib.h"
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#else
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#include "arch/i86/x86_64/cacheX86_64.h"
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#endif /* CPU==LP64 */
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#endif /* CPU_FAMILY == I80X86 */
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#if (CPU_FAMILY == AM29XXX)
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#include "arch/am29k/cacheAm29kLib.h"
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#endif /* CPU_FAMILY == AM29XXX */
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#if (CPU_FAMILY == SH)
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#include "arch/sh/cacheShLib.h"
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#endif /* CPU_FAMILY == SH */
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#if (CPU_FAMILY == ARM)
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#include "arch/arm/cacheArmLib.h"
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#endif /* CPU_FAMILY == ARM */
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#endif /* __INCcacheLibh */
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