355 lines
13 KiB
C
355 lines
13 KiB
C
/* regsSimnt.h - simnt registers header */
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/*
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* Copyright (c) 1997-1998,2003-2004,2006-2008,2010,2011
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* Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use of this
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* software may be licensed only pursuant to the terms of an applicable
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* Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01w,05sep11,elp added CPUID type and definitions (CQID: WIND00286339).
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01v,24jun11,elp added fsBase to regset for tools (CQ:WIND00278823).
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01u,04jan11,elp added simulator specific TCB for fsBase (CQ:WINd00247541).
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01t,29jul10,elp fixed VXSIM_SIMSTATUS_VALUE_GET()
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01s,18jun10,elp added address register in VXSIM_SIMSTATUS_VALUE_GET().
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01r,13apr10,elp added ELFAGS_BRANDNEW define, replaced ULONG by VXSIM_ULONG.
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01q,29apr10,pad Moved extern C statement after include statements.
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01p,01mar10,elp 64bits support.
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01o,27may08,elp fixed warnings.
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01n,05jan07,elp added pSimStatus and pSimIntPendingLvl declarations,
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added interrupt level macros.
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01m,17oct06,elp added WIND_CPU_STATE.
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01l,31aug04,jmp made SIMLINUX REG_SET indentical to SIMNT.
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01k,01dec03,jmp added mmuTransTbl (current MMU translation table) to REG_SET.
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01j,24nov03,jeg added macros to manage supervisor bit
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01i,14nov03,jmp added SIM_STATUS_USR.
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01h,18sep03,jeg removed SIM_STATUS_INIT macro.
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01g,12sep03,jeg updated REG_SET structure to split intLockKey by a status bit
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field. Removed the WIND_TCB_* macros.
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01f,27may03,jmp added Register offsets in TCB.
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01e,26mar03,jmp replaced INSTR by UCHAR to use this file from host side.
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01d,17mar03,jmp renamed macros REG_* in REG_SET_*.
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01c,16jan03,elp added REGS defines (SPR #84278).
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01b,29apr98,cym added intLockKey
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01a,27aug97,cym written
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*/
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#ifndef __INCregsSimnth
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#define __INCregsSimnth
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#ifndef HOST
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#include <vsbConfig.h>
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#include <types/vxArch.h>
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#endif /* HOST */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define EFLAGS_BRANDNEW 0x10202
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#ifdef _WRS_CONFIG_LP64
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#ifndef _ASMLANGUAGE
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#define GREG_NUM 16 /* has 64-bit general registers */
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typedef struct /* REG_SET - simnt register set (based on x86_64) */
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{
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UINT32 reg_status; /* status bit field */
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UINT32 unused;
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VXSIM_ULONG mmuTransTbl; /* current MMU translation table */
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VXSIM_ULONG r15; /* general register */
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VXSIM_ULONG r14; /* general register */
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VXSIM_ULONG r13; /* general register */
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VXSIM_ULONG r12; /* general register */
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VXSIM_ULONG r11; /* general register */
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VXSIM_ULONG r10; /* general register */
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VXSIM_ULONG r9; /* general register */
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VXSIM_ULONG r8; /* general register */
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VXSIM_ULONG rdi; /* general register */
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VXSIM_ULONG rsi; /* general register */
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VXSIM_ULONG rbp; /* frame pointer register */
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VXSIM_ULONG rsp; /* stack pointer register */
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VXSIM_ULONG rbx; /* general register */
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VXSIM_ULONG rdx; /* general register */
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VXSIM_ULONG rcx; /* general register */
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VXSIM_ULONG rax; /* general register */
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VXSIM_ULONG rflags; /* status register */
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UCHAR * pc; /* program counter */
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VXSIM_ULONG fsBase; /* fsBase for tool easy access,
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* synchronized with extraRegs value when saving,
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* never used when loading */
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} REG_SET;
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typedef struct /* SIM_REG_SET - simulator specific part of TCB */
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{
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VXSIM_ULONG fsBase;
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} SIM_REG_SET;
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/* some common names for registers */
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#undef spReg
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#undef pc
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#define fpReg rbp /* frame pointer */
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#define spReg rsp /* stack pointer */
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#define flReg rflags /* flags register */
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#define eflags rflags
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#define reg_pc pc
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#define reg_sp spReg
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#define reg_fp fpReg
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#define G_REG_BASE 0x10 /* data reg's base offset to REG_SET */
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#define G_REG_OFFSET(n) (G_REG_BASE + (n) * sizeof(VXSIM_ULONG))
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#define SR_OFFSET G_REG_OFFSET(GREG_NUM)
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#define PC_OFFSET (SR_OFFSET + sizeof(VXSIM_ULONG))
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#else /* _ASMLANGUAGE */
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#define VXSIM_SIMSTATUS_ADDR_GET(reg) \
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movabsq $VAR(pSimStatus),reg; \
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mov (reg),reg
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#define VXSIM_SIMSTATUS_VALUE_GET(addrRegSuffix,valRegSuffix) \
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movabsq $VAR(pSimStatus),%r##addrRegSuffix; \
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mov (%r##addrRegSuffix), %r##addrRegSuffix; \
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movl 0x0(%r##addrRegSuffix),%e##valRegSuffix;
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#endif /* _ASMLANGUAGE */
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/* Register offsets */
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#define REG_SET_SIMSTATUS 0x00
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#define REG_SET_MMU_TRANS_TBL 0x08
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#define REG_SET_R15 0x10
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#define REG_SET_R14 0x18
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#define REG_SET_R13 0x20
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#define REG_SET_R12 0x28
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#define REG_SET_R11 0x30
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#define REG_SET_R10 0x38
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#define REG_SET_R9 0x40
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#define REG_SET_R8 0x48
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#define REG_SET_RDI 0x50
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#define REG_SET_RSI 0x58
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#define REG_SET_RBP 0x60
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#define REG_SET_RSP 0x68
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#define REG_SET_RBX 0x70
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#define REG_SET_RDX 0x78
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#define REG_SET_RCX 0x80
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#define REG_SET_RAX 0x88
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#define REG_SET_RFLAGS 0x90
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#define REG_SET_RIP 0x98
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#define REG_SET_PC 0x98
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#else /* _WRS_CONFIG_LP64 */
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#ifndef _ASMLANGUAGE
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#define GREG_NUM 8
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typedef struct /* REG_SET - simnt register set (based on x86) */
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{
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VXSIM_ULONG edi; /* general register */
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VXSIM_ULONG esi; /* general register */
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VXSIM_ULONG ebp; /* general register */
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VXSIM_ULONG esp; /* general register */
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VXSIM_ULONG ebx; /* general register */
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VXSIM_ULONG edx; /* general register */
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VXSIM_ULONG ecx; /* frame pointer register */
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VXSIM_ULONG eax; /* stack pointer register */
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VXSIM_ULONG eflags; /* status register */
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UCHAR * pc; /* program counter */
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VXSIM_ULONG reg_status; /* status bit field */
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UINT32 mmuTransTbl; /* current MMU translation table */
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char unused[0xc8]; /* unused - keep for SIMNT backward */
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/* compatibility with T2.x releases */
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} REG_SET;
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#undef spReg
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#undef pc
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#define spReg esp
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#define fpReg ebp
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#define flReg eflags
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#define reg_pc pc
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#define reg_sp spReg
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#define reg_fp fpReg
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#define G_REG_BASE 0x00 /* data reg's base offset to REG_SET */
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#define G_REG_OFFSET(n) (G_REG_BASE + (n) * sizeof(VXSIM_ULONG))
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#define SR_OFFSET G_REG_OFFSET(GREG_NUM)
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#define PC_OFFSET (SR_OFFSET + sizeof(VXSIM_ULONG))
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#else /* _ASMLANGUAGE */
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#define VXSIM_SIMSTATUS_ADDR_GET(reg) \
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movl VAR(pSimStatus),reg; \
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#define VXSIM_SIMSTATUS_VALUE_GET(addrRegSuffix,valRegSuffix) \
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movl VAR(pSimStatus),%e##addrRegSuffix; \
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movl 0x0(%e##addrRegSuffix),%e##valRegSuffix;
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#endif /* _ASMLANGUAGE */
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/* Register offsets */
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#define REG_SET_EDI 0x00
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#define REG_SET_ESI 0x04
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#define REG_SET_EBP 0x08
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#define REG_SET_ESP 0x0c
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#define REG_SET_EBX 0x10
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#define REG_SET_EDX 0x14
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#define REG_SET_ECX 0x18
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#define REG_SET_EAX 0x1c
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#define REG_SET_EFLAGS 0x20
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#define REG_SET_PC 0x24
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#define REG_SET_SIMSTATUS 0x28
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#define REG_SET_MMU_TRANS_TBL 0x2c
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#endif /* _WRS_CONFIG_LP64 */
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#ifndef _ASMLANGUAGE
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typedef struct wind_cpu_state /* CPU initial state */
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{
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REG_SET regs; /* initial register set */
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} WIND_CPU_STATE;
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typedef struct cpuid /* CPUID - 80x86 cpuid version/feature */
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{
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int highestValue; /* EAX=0: highest integer value */
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int vendorId[3]; /* EAX=0: vendor identification string */
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int signature; /* EAX=1: processor signature */
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int featuresEbx; /* EAX=1: feature flags EBX */
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int featuresEcx; /* EAX=1: feature flags ECX */
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int featuresEdx; /* EAX=1: feature flags EDX */
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int cacheEax; /* EAX=2: config parameters EAX */
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int cacheEbx; /* EAX=2: config parameters EBX */
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int cacheEcx; /* EAX=2: config parameters ECX */
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int cacheEdx; /* EAX=2: config parameters EDX */
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int serialNo64[2]; /* EAX=3: lower 64 of 96 bit serial no */
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int brandString[12]; /* EAX=0x8000000[234]: brand strings */
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} CPUID;
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extern volatile UINT32 * pSimStatus;
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extern volatile UINT32 * pSimIntPendingLvl;
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#define VXSIM_PENDING_INT_CHECK(minLvl) \
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((*pSimIntPendingLvl) > (minLvl))
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#endif /* _ASMLANGUAGE */
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/* status bit fields */
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#define SIM_STATUS_INTLOCK 0x0001 /* interrupt locked */
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#define SIM_STATUS_INTUNLOCK 0x0000 /* interrupt unlocked */
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#define SIM_STATUS_SUP 0x0002 /* supervisor mode */
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#define SIM_STATUS_USR 0x0000 /* user mode */
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#define SIM_STATUS_INTLVL_MASK 0x0f00 /* interrupt level mask */
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#define SIM_STATUS_INTLVL_SHIFT 8
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/* macros to access interrupt status field */
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#define VXSIM_INT_MASK_SET(vxsimStatus) \
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(vxsimStatus |= SIM_STATUS_INTLOCK)
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#define VXSIM_INT_MASK_CLEAR(vxsimStatus) \
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(vxsimStatus &= ~(SIM_STATUS_INTLOCK))
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#define VXSIM_INT_MASK_GET(vxsimStatus) \
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(((vxsimStatus & SIM_STATUS_INTLOCK) == 0) ? FALSE : TRUE)
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#define VXSIM_SUP_MODE_SET(vxsimStatus) \
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(vxsimStatus |= SIM_STATUS_SUP)
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#define VXSIM_USR_MODE_SET(vxsimStatus) \
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(vxsimStatus &= ~(SIM_STATUS_SUP))
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#define VXSIM_SUP_MODE_GET(vxsimStatus) \
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(((vxsimStatus & SIM_STATUS_SUP) == 0) ? FALSE : TRUE)
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#define VXSIM_INT_LVL_GET(vxsimStatus) \
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(((vxsimStatus & SIM_STATUS_INTLVL_MASK) >> SIM_STATUS_INTLVL_SHIFT))
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#define VXSIM_INT_LVL_SET(vxsimStatus,intLvl) \
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(vxsimStatus = (vxsimStatus & ~SIM_STATUS_INTLVL_MASK) | \
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((intLvl << SIM_STATUS_INTLVL_SHIFT) & \
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SIM_STATUS_INTLVL_MASK))
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#define VX_CPUID_HIGHVALUE 0 /* offset to highestValue */
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#define VX_CPUID_VENDORID 4 /* offset to vendorId */
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#define VX_CPUID_SIGNATURE 16 /* offset to signature */
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#define VX_CPUID_FEATURES_EBX 20 /* offset to featuresEbx */
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#define VX_CPUID_FEATURES_ECX 24 /* offset to featuresEcx */
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#define VX_CPUID_FEATURES_EDX 28 /* offset to featuresEdx */
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#define VX_CPUID_CACHE_EAX 32 /* offset to cacheEax */
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#define VX_CPUID_CACHE_EBX 36 /* offset to cacheEbx */
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#define VX_CPUID_CACHE_ECX 40 /* offset to cacheEcx */
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#define VX_CPUID_CACHE_EDX 44 /* offset to cacheEdx */
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#define VX_CPUID_SERIALNO 48 /* offset to serialNo64 */
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#define VX_CPUID_BRAND_STR 56 /* offset to brandString[0] */
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#define VX_CPUID_HIGHVALUE_EXT 104 /* offset to highestValue Extended */
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#define VX_CPUID_EXT_FEATURES_EDX 108 /* offset to featuresEdx Extended */
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#define VX_CPUID_EXT_FEATURES_ECX 112 /* offset to featuresEcx Extended */
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#define VX_CPUID_CACHE_COUNT 116 /* offset to cache count */
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#define VX_CPUID_CACHE_PARAMS 120 /* offset to cache parameters */
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#define VX_CPUID_MONITOR_EAX 216 /* offset to montor/mwait parameters */
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#define VX_CPUID_MONITOR_EBX 220 /* offset to montor/mwait parameters */
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#define VX_CPUID_MONITOR_ECX 224 /* offset to montor/mwait parameters */
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#define VX_CPUID_MONITOR_EDX 228 /* offset to montor/mwait parameters */
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#define VX_CPUID_DTSPM_EAX 232 /* offset to DTSPM parameters */
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#define VX_CPUID_DTSPM_EBX 236 /* offset to DTSPM parameters */
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#define VX_CPUID_DTSPM_ECX 240 /* offset to DTSPM parameters */
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#define VX_CPUID_DTSPM_EDX 244 /* offset to DTSPM parameters */
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#define VX_CPUID_DCA_EAX 248 /* offset to DCA parameters */
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#define VX_CPUID_PMON_EAX 252 /* offset to PMON parameters */
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#define VX_CPUID_PMON_EBX 256 /* offset to PMON parameters */
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#define VX_CPUID_PMON_ECX 260 /* offset to PMON parameters */
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#define VX_CPUID_PMON_EDX 264 /* offset to PMON parameters */
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#define VX_CPUID_PTOP_COUNT 268 /* offset to PTOP count */
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#define VX_CPUID_PTOP_PARAMS 272 /* offset to PTOP parameters */
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#define VX_CPUID_XSAVE_EAX 336 /* offset to XSAVE parameters */
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#define VX_CPUID_XSAVE_EBX 340 /* offset to XSAVE parameters */
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#define VX_CPUID_XSAVE_ECX 344 /* offset to XSAVE parameters */
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#define VX_CPUID_XSAVE_EDX 348 /* offset to XSAVE parameters */
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#define VX_CPUID_L2CACHE_EAX 352 /* offset to L2 Cache parameters */
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#define VX_CPUID_L2CACHE_EBX 356 /* offset to L2 Cache parameters */
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#define VX_CPUID_L2CACHE_ECX 360 /* offset to L2 Cache parameters */
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#define VX_CPUID_L2CACHE_EDX 364 /* offset to L2 Cache parameters */
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#define VX_CPUID_APM_EAX 368 /* offset to Advanced Power Mgt parameters */
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#define VX_CPUID_APM_EBX 372 /* offset to Advanced Power Mgt parameters */
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#define VX_CPUID_APM_ECX 376 /* offset to Advanced Power Mgt parameters */
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#define VX_CPUID_APM_EDX 380 /* offset to Advanced Power Mgt parameters */
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#define VX_CPUID_VPADRS_EAX 384 /* offset to Virt/Phys Adr Size parameters */
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#define VX_CPUID_VPADRS_EBX 388 /* offset to Virt/Phys Adr Size parameters */
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#define VX_CPUID_VPADRS_ECX 392 /* offset to Virt/Phys Adr Size parameters */
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#define VX_CPUID_VPADRS_EDX 396 /* offset to Virt/Phys Adr Size parameters */
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/* bit mask in VX_CPUID_FEATURES structure */
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#define VX_CPUID_FPU 0x00000001
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#define VX_CPUID_MMX 0x00800000
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#define VX_CPUID_FXSR 0x01000000
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#define VX_CPUID_SSE 0x02000000
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#define VX_CPUID_SSE2 0x04000000
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/* bit mask in VX_CPUID_FEATURES_EXT structure */
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#define VX_CPUID_SSE3 0x00000001
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#define VX_CPUID_SSE42 0x00100000
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#define VX_CPUID_XSAVE 0x04000000
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#define VX_CPUID_OSXSAVE 0x08000000
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#define VX_CPUID_AVX 0x10000000
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCregsSimnth */
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