530 lines
25 KiB
C
530 lines
25 KiB
C
/* dga001Vme.h - Densan DGA-001 VMEbus Interface Controller */
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/* Copyright 1994-1997 Wind River Systems, Inc. */
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#include "copyright_wrs.h"
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/*
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modification history
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--------------------
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01l,12jul97,hk renamed as dga001Vme.h from drv/multi/dga001.h.
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01k,15jan96,hk added support for DVE-SH7043.
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01j,10nov95,hk changed CSR to DGA_CSR.
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01i,09nov95,hk fixed CSR1_1_RRS, but not used. did some code reviewing.
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01h,04jul95,hk modified some macro names.
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01g,07jun95,hk changed CSR20/CSR21 bit defs. copyright to '95.
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01f,15dec94,sa wrote CSR13_0, CSR15_0, CSR16_0, CSR17, IFR0, IFR1, IFR3.
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01e,14nov94,hk wrote CSR18_1.
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01d,09nov94,sa write CSR12, CSR14 and CSR23.
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01c,19oct94,sa write CSR19 to CSR21
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01b,08sep94,sa write to CSR7
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01a,07sep94,sa derived from 01e of vmechip.h.
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*/
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#ifdef DOC
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#define INCdga001Vmeh
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#endif /* DOC */
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#ifndef __INCdga001Vmeh
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#define __INCdga001Vmeh
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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This file contains constants for the Densan DGA-001 VMEbus Interface.
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The macro DGA001_BASE_ADRS must be defined when using local bus addresses
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defined in this header. The macro IFR_BUS_BASE_ADRS must be defined when
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using VMEbus addresses defined in this header.
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The following standards have been adopted in the creation of this file.
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Registers in the CSR have the prefix "DGA_CSR". And "DGA_CSR0_0" means most
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low address of CSR0 register.
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Registers in the IFR have the prefix "DGA_IFR" when addressed locally and
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the prefix "IFR_BUS" when addressed from the VMEbus. The bit definitions
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are shared.
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The registers are listed in ascending (numerical) order; the definitions
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for each register start with a header, e.g.:
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Register Register Register Register
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Mnemonic Number Address Name
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v v v v
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/@***********************************************************************
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* CSR0_0 0x00 0x00 local bus control and status*
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***********************************************************************@/
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The format of the definitions is as follows. The define name always
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starts with the register mnemonic it is associated with. The [7-0]
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number at the end of the comment indicates the bit position to which the
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the define applies. In the definition of PURSTF, for example, the 7
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indicates bit 7:
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v
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#define CSR1_0_PURSTF 0x80 /@ power-up status bit 7 @/
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If the define applies to more than one bit, then the applicable bit
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range is specified by two digits. In the following example,
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CSR0_LBT applies to the two bit field, bits 5-4:
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v
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#define CSR0_0_LBT 0x10 /@ local bus time-out (mask) 54 @/
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If no bit field is given, then the define applies to the whole register.
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*/
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#define DGA001_LONG_ADRS(offset) \
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((volatile UINT32 *)(DGA001_BASE_ADRS + offset))
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#if defined(TARGET_DVE7604) || defined(TARGET_DVE7043)
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#define DGA001_BYTE_ADRS(offset) \
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((volatile UINT8 *)(DGA001_BASE_ADRS + DGA001_BYTE_ACCESS_OFFSET + offset))
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#else
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#define DGA001_BYTE_ADRS(offset) \
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((volatile UINT8 *)(DGA001_BASE_ADRS + offset))
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#endif /* TARGET_DVE7604 */
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/*
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* Control and Status Register (CSR) definitions.
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*
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* only the local CPU can access the LCSR.
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*/
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#define DGA_CSR0 DGA001_LONG_ADRS(0x00)
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#define DGA_CSR0_0 DGA001_BYTE_ADRS(0x00)
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#define DGA_CSR0_1 DGA001_BYTE_ADRS(0x01)
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#define DGA_CSR0_2 DGA001_BYTE_ADRS(0x02)
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#define DGA_CSR0_3 DGA001_BYTE_ADRS(0x03)
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#define DGA_CSR1 DGA001_LONG_ADRS(0x04)
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#define DGA_CSR1_0 DGA001_BYTE_ADRS(0x04)
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#define DGA_CSR1_1 DGA001_BYTE_ADRS(0x05)
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#define DGA_CSR1_2 DGA001_BYTE_ADRS(0x06)
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#define DGA_CSR1_3 DGA001_BYTE_ADRS(0x07)
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#define DGA_CSR2 DGA001_LONG_ADRS(0x08)
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#define DGA_CSR2_0 DGA001_BYTE_ADRS(0x08)
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#define DGA_CSR2_1 DGA001_BYTE_ADRS(0x09)
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#define DGA_CSR2_2 DGA001_BYTE_ADRS(0x0a)
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#define DGA_CSR2_3 DGA001_BYTE_ADRS(0x0b)
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#define DGA_CSR3 DGA001_LONG_ADRS(0x0c)
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#define DGA_CSR3_0 DGA001_BYTE_ADRS(0x0c)
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#define DGA_CSR3_1 DGA001_BYTE_ADRS(0x0d)
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#define DGA_CSR3_2 DGA001_BYTE_ADRS(0x0e)
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#define DGA_CSR3_3 DGA001_BYTE_ADRS(0x0f)
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#define DGA_CSR4 DGA001_LONG_ADRS(0x10)
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#define DGA_CSR4_0 DGA001_BYTE_ADRS(0x10)
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#define DGA_CSR4_1 DGA001_BYTE_ADRS(0x11)
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#define DGA_CSR4_2 DGA001_BYTE_ADRS(0x12)
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#define DGA_CSR4_3 DGA001_BYTE_ADRS(0x13)
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#define DGA_CSR5 DGA001_LONG_ADRS(0x14)
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#define DGA_CSR5_0 DGA001_BYTE_ADRS(0x14)
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#define DGA_CSR5_1 DGA001_BYTE_ADRS(0x15)
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#define DGA_CSR5_2 DGA001_BYTE_ADRS(0x16)
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#define DGA_CSR5_3 DGA001_BYTE_ADRS(0x17)
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#define DGA_CSR6 DGA001_LONG_ADRS(0x18)
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#define DGA_CSR6_0 DGA001_BYTE_ADRS(0x18)
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#define DGA_CSR6_1 DGA001_BYTE_ADRS(0x19)
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#define DGA_CSR6_2 DGA001_BYTE_ADRS(0x1a)
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#define DGA_CSR6_3 DGA001_BYTE_ADRS(0x1b)
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#define DGA_CSR7 DGA001_LONG_ADRS(0x1c)
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#define DGA_CSR7_0 DGA001_BYTE_ADRS(0x1c)
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#define DGA_CSR7_1 DGA001_BYTE_ADRS(0x1d)
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#define DGA_CSR7_2 DGA001_BYTE_ADRS(0x1e)
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#define DGA_CSR7_3 DGA001_BYTE_ADRS(0x1f)
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#define DGA_CSR8 DGA001_LONG_ADRS(0x21)
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#define DGA_CSR9 DGA001_LONG_ADRS(0x24)
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#define DGA_CSR10 DGA001_LONG_ADRS(0x28)
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#define DGA_CSR10_0 DGA001_BYTE_ADRS(0x28)
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#define DGA_CSR10_1 DGA001_BYTE_ADRS(0x29)
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#define DGA_CSR10_2 DGA001_BYTE_ADRS(0x2a)
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#define DGA_CSR10_3 DGA001_BYTE_ADRS(0x2b)
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#define DGA_CSR11 DGA001_LONG_ADRS(0x2c)
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#define DGA_CSR11_0 DGA001_BYTE_ADRS(0x2c)
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#define DGA_CSR11_1 DGA001_BYTE_ADRS(0x2d)
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#define DGA_CSR11_2 DGA001_BYTE_ADRS(0x2e)
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#define DGA_CSR11_3 DGA001_BYTE_ADRS(0x2f)
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#define DGA_CSR12 DGA001_LONG_ADRS(0x30)
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#define DGA_CSR13 DGA001_LONG_ADRS(0x34)
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#define DGA_CSR14 DGA001_LONG_ADRS(0x38)
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#define DGA_CSR15 DGA001_LONG_ADRS(0x3c)
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#define DGA_CSR16 DGA001_LONG_ADRS(0x40)
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#define DGA_CSR17 DGA001_LONG_ADRS(0x44)
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#define DGA_CSR18 DGA001_LONG_ADRS(0x48)
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#define DGA_CSR18_1 DGA001_BYTE_ADRS(0x49)
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#define DGA_CSR18_2 DGA001_BYTE_ADRS(0x4a)
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#define DGA_CSR18_3 DGA001_BYTE_ADRS(0x4b)
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#define DGA_CSR19 DGA001_LONG_ADRS(0x4c)
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#define DGA_CSR19_0 DGA001_BYTE_ADRS(0x4c)
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#define DGA_CSR19_1 DGA001_BYTE_ADRS(0x4d)
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#define DGA_CSR19_2 DGA001_BYTE_ADRS(0x4e)
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#define DGA_CSR19_3 DGA001_BYTE_ADRS(0x4f)
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#define DGA_CSR20 DGA001_LONG_ADRS(0x50)
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#define DGA_CSR21 DGA001_LONG_ADRS(0x54)
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#define DGA_CSR22 DGA001_LONG_ADRS(0x58)
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#define DGA_CSR23 DGA001_LONG_ADRS(0x5c)
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#define DGA_CSR24 DGA001_LONG_ADRS(0x60)
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#define DGA_CSR25 DGA001_LONG_ADRS(0x64)
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#define DGA_CSR26 DGA001_LONG_ADRS(0x68)
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#define DGA_CSR27 DGA001_LONG_ADRS(0x6c)
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/*
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* Interface Register (IFR) definitions.
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*
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* All registers of the IFR are accessible to both the local processor
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* and to other VMEbus masters.
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*/
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#define DGA_IFR0 DGA001_LONG_ADRS(0x70)
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#define DGA_IFR1 DGA001_LONG_ADRS(0x74)
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#define DGA_IFR2 DGA001_LONG_ADRS(0x78)
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#define DGA_IFR3 DGA001_LONG_ADRS(0x7c)
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/*************************************************************************
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* CSR0_0 0x00 0x00 local bus control *
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*************************************************************************/
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#define CSR0_0_LBT_DIS 0x30 /* local bus time-out disable 5-4 */
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#define CSR0_0_LBT_256 0x20 /* local bus time-out 256 clks 5-4 */
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#define CSR0_0_LBT_128 0x10 /* local bus time-out 128 clks 5-4 */
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#define CSR0_0_LBT_64 0x00 /* local bus time-out 64 clks 5-4 */
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#define CSR0_0_TAOUTE 0x08 /* local bus TAOUT enable 3 */
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/*************************************************************************
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* CSR0_1 0x00 0x01 bus error control and status *
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*************************************************************************/
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#define CSR0_1_BERDYO 0x80 /* activate RDYO# upon bus error 7 */
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#define CSR0_1_LBTOUT 0x04 /* local bus time-out (status) 2 */
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#define CSR0_1_RQTOUT 0x02 /* request time-out (status) 1 */
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#define CSR0_1_VMEBERR 0x01 /* VMEbus bus error (status) 0 */
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/*************************************************************************
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* CSR0_2 0x00 0x02 general purpose output enable *
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*************************************************************************/
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#define CSR0_2_GPOE7 0x80 /* general purpose output 7 enable 7 */
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#define CSR0_2_GPOE6 0x40 /* general purpose output 6 enable 6 */
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#define CSR0_2_GPOE5 0x20 /* general purpose output 5 enable 5 */
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#define CSR0_2_GPOE4 0x10 /* general purpose output 4 enable 4 */
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#define CSR0_2_GPOE3 0x08 /* general purpose output 3 enable 3 */
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#define CSR0_2_GPOE2 0x04 /* general purpose output 2 enable 2 */
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#define CSR0_2_GPOE1 0x02 /* general purpose output 1 enable 1 */
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#define CSR0_2_GPOE0 0x01 /* general purpose output 0 enable 0 */
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/*************************************************************************
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* CSR0_3 0x00 0x03 general purpose I/O *
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*************************************************************************/
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#define CSR0_3_GPIO7 0x80 /* general purpose I/O 7 7 */
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#define CSR0_3_GPIO6 0x40 /* general purpose I/O 6 6 */
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#define CSR0_3_GPIO5 0x20 /* general purpose I/O 5 5 */
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#define CSR0_3_GPIO4 0x10 /* general purpose I/O 4 4 */
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#define CSR0_3_GPIO3 0x08 /* general purpose I/O 3 3 */
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#define CSR0_3_GPIO2 0x04 /* general purpose I/O 2 2 */
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#define CSR0_3_GPIO1 0x02 /* general purpose I/O 1 1 */
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#define CSR0_3_GPIO0 0x01 /* general purpose I/O 0 0 */
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/*************************************************************************
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* CSR1_0 0x01 0x04 reset control and status *
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*************************************************************************/
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#define CSR1_0_PURSTF 0x80 /* power-up reset (status) 7 */
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#define CSR1_0_RSWEN 0x40 /* reset switch enable 6 */
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#define CSR1_0_RSWSYS 0x20 /* VMEbus SYSRESET enable 5 */
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/*************************************************************************
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* CSR1_1 0x01 0x05 system controller configuration *
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*************************************************************************/
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#define CSR1_1_SYSCON 0x80 /* system controller (status) 7 */
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#define CSR1_1_RRS 0x10 /* round robin arbitration 4 */
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#define CSR1_1_PRI 0x00 /* prioritized arbitration 4 */
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#define CSR1_1_ARBT_DIS 0x0c /* arbitration time-out disable 3-2 */
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#define CSR1_1_ARBT_63 0x08 /* arbitration time-out 63 usec 3-2 */
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#define CSR1_1_ARBT_31 0x04 /* arbitration time-out 31 usec 3-2 */
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#define CSR1_1_ARBT_15 0x00 /* arbitration time-out 15 usec 3-2 */
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#define CSR1_1_SBT_DIS 0x03 /* VME bus time-out disable 1-0 */
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#define CSR1_1_SBT_511 0x02 /* VME bus time-out 511 usec 1-0 */
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#define CSR1_1_SBT_255 0x01 /* VME bus time-out 255 usec 1-0 */
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#define CSR1_1_SBT_127 0x00 /* VME bus time-out 127 usec 1-0 */
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/*************************************************************************
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* CSR1_2 0x01 0x06 VMEbus requester control *
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*************************************************************************/
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#define CSR1_2_DWB 0x80 /* VMEbus request 7 */
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#define CSR1_2_OWN 0x40 /* VMEbus request (status) 6 */
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#define CSR1_2_RQT_DIS 0x30 /* request time-out disable 5-4 */
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#define CSR1_2_RQT_1023 0x20 /* request time-out 1023 usec 5-4 */
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#define CSR1_2_RQT_511 0x10 /* request time-out 511 usec 5-4 */
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#define CSR1_2_RQT_255 0x00 /* request time-out 255 usec 5-4 */
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#define CSR1_2_RNV 0x0c /* release never 3-2 */
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#define CSR1_2_RBC 0x08 /* release when bus clear 3-2 */
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#define CSR1_2_RWD 0x04 /* release when done 3-2 */
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#define CSR1_2_ROR 0x00 /* release on request 3-2 */
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#define CSR1_2_BR3 0x03 /* VMEbus request level 3 1-0 */
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#define CSR1_2_BR2 0x02 /* VMEbus request level 2 1-0 */
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#define CSR1_2_BR1 0x01 /* VMEbus request level 1 1-0 */
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#define CSR1_2_BR0 0x00 /* VMEbus request level 0 1-0 */
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/*************************************************************************
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* CSR1_3 0x01 0x07 VMEbus master control *
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*************************************************************************/
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#define CSR1_3_RMC 0x80 /* read-modify-write cycle 7 */
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#define CSR1_3_AAMEN 0x40 /* addess modifier code enable 6 */
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#define CSR1_3_AAMDIS 0x00 /* addess modifier code disable 6 */
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#define CSR1_3_AAM 0x3f /* addess modifier code (mask) 5-0 */
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/*************************************************************************
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* CSR2_0 0x02 0x08 unused *
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* to *
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* CSR3_1 0x03 0x0d unused *
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*************************************************************************/
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/*************************************************************************
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* CSR3_2 0x03 0x0e interface register address *
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*************************************************************************/
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#define CSR3_2_IFRA_H 0xff /* interface register addess (mask) 7-0 */
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/*************************************************************************
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* CSR3_3 0x03 0x0f interface register address *
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*************************************************************************/
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#define CSR3_3_IFRA_L 0xf0 /* interface register addess (mask) 7-4 */
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#define CSR3_3_IFRSUP 0x02 /* respond to supervisor 1 */
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#define CSR3_3_IFRUSR 0x01 /* respond to user 0 */
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/*************************************************************************
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* CSR4_01 0x04 0x10 slave address 0 *
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*************************************************************************/
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#define CSR4_01_SL0A 0xffff /* slave addess 0 (mask) 15-0 */
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/*************************************************************************
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* CSR4_23 0x04 0x12 address mask 0 *
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*************************************************************************/
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#define CSR4_23_AM0A 0xffff /* address mask 0 (mask) 15-0 */
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/*************************************************************************
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* CSR5_01 0x05 0x14 mapping address 0 *
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*************************************************************************/
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#define CSR5_01_MP0A 0xffff /* mapping address 0 (mask) 15-0 */
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/*************************************************************************
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* CSR5_23 0x05 0x16 slave control 0 *
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*************************************************************************/
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#define CSR5_23_A32EN0 0x0020 /* respond to extended 5 */
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#define CSR5_23_A24EN0 0x0010 /* respond to standard 4 */
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#define CSR5_23_SUPER0 0x0008 /* respond to supervisor 3 */
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#define CSR5_23_USER0 0x0004 /* respond to user 2 */
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#define CSR5_23_PRGRM0 0x0002 /* respond to program 1 */
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#define CSR5_23_DATA0 0x0001 /* respond to data 0 */
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/*************************************************************************
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* CSR6_01 0x06 0x18 save address 1 *
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*************************************************************************/
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#define CSR6_01_SL0A 0xffff /* slave addess 1 (mask) 15-0 */
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/*************************************************************************
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* CSR6_23 0x06 0x1a address mask 1 *
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*************************************************************************/
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#define CSR6_23_AM0A 0xffff /* address mask 1 (mask) 15-0 */
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/*************************************************************************
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* CSR7_01 0x07 0x1c mapping addess 1 *
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*************************************************************************/
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#define CSR7_01_MP0A 0xffff /* mapping address 1 (mask) 15-0 */
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/*************************************************************************
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* CSR7_23 0x07 0x1e slave control 1 *
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*************************************************************************/
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#define CSR7_23_A32EN0 0x0020 /* respond to extended 5 */
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#define CSR7_23_A24EN0 0x0010 /* respond to standard 4 */
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#define CSR7_23_SUPER0 0x0008 /* respond to supervisor 3 */
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#define CSR7_23_USER0 0x0004 /* respond to user 2 */
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#define CSR7_23_PRGRM0 0x0002 /* respond to program 1 */
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#define CSR7_23_DATA0 0x0001 /* respond to data 0 */
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/*************************************************************************
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* CSR12 0x0c 0x30 tick timer 0 control *
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*************************************************************************/
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#define CSR12_TT0CEN 0x80000000 /* tick timer 0 enable */
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/*************************************************************************
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* CSR13 0x0d 0x34 tick timer 0 counter *
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*************************************************************************/
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#define CSR13_TT0OCL 0x80000000 /* overflow counter clear */
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/*************************************************************************
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* CSR14 0x0e 0x38 tick timer 1 control *
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*************************************************************************/
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#define CSR14_TT1CEN 0x80000000 /* tick timer 1 enable */
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/*************************************************************************
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* CSR15 0x0f 0x3c tick timer 1 counter *
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*************************************************************************/
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#define CSR15_TT1OCL 0x80000000 /* overflow counter clear */
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/*************************************************************************
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* CSR16 0x10 0x40 watchdog timer control *
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*************************************************************************/
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#define CSR16_WDTCEN 0x80000000 /* watchdog timer enable */
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#define CSR16_WDTSFE 0x40000000 /* watchdog timer SYSFAIL enable*/
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/*************************************************************************
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* CSR17 0x11 0x44 watchdog timer counter *
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*************************************************************************/
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#define CSR17_WDTCLR 0x80000000 /* watchdog timer counter clear */
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#define CSR17_WDTOUT 0x01000000 /* watchdog timeout (status) */
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/*************************************************************************
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* CSR18_1 0x12 0x49 interrupt sense mode control *
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*************************************************************************/
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#define CSR18_1_ACFLVL 0x80 /* ACFAIL int level(1)/edge(0) sense 7 */
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#define CSR18_1_ABTLVL 0x40 /* ABORT int level(1)/edge(0) sense 6 */
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#define CSR18_1_SFLVL 0x20 /* SYSFAIL int level(1)/edge(0) sense 5 */
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/*************************************************************************
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* CSR20 0x14 0x50 interrupt status *
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*************************************************************************/
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#define CSR20_ACFIRQ 0x80000000 /* ACFAIL interrupt 31 */
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#define CSR20_ABTIRQ 0x40000000 /* ABORT interrupt 30 */
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#define CSR20_SFIRQ 0x20000000 /* SYSFAIL interrupt 29 */
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#define CSR20_BERIRQ 0x10000000 /* BERR interrupt 28 */
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#define CSR20_IAKIRQ 0x08000000 /* IAK interrupt 27 */
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#define CSR20_SRQIRQ 0x04000000 /* SRQ interrupt 26 */
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#define CSR20_SAKIRQ 0x02000000 /* SAKF interrupt 25 */
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#define CSR20_GP7IRQ 0x00800000 /* GP7 interrupt 23 */
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#define CSR20_DMAIRQ 0x00400000 /* DMA interrupt 22 */
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#define CSR20_TT1IRQ 0x00200000 /* TT1 interrupt 21 */
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#define CSR20_TT0IRQ 0x00100000 /* TT0 interrupt 20 */
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#define CSR20_GP3IRQ 0x00080000 /* GP3 interrupt 19 */
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#define CSR20_GP2IRQ 0x00040000 /* GP2 interrupt 18 */
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#define CSR20_GP1IRQ 0x00020000 /* GP1 interrupt 17 */
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#define CSR20_GP0IRQ 0x00010000 /* GP0 interrupt 16 */
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#define CSR20_SWIRQ7 0x00008000 /* SWIRQ7 interrupt 15 */
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#define CSR20_SWIRQ6 0x00004000 /* SWIRQ6 interrupt 14 */
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#define CSR20_SWIRQ5 0x00002000 /* SWIRQ5 interrupt 13 */
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#define CSR20_SWIRQ4 0x00001000 /* SWIRQ4 interrupt 12 */
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#define CSR20_SWIRQ3 0x00000800 /* SWIRQ3 interrupt 11 */
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#define CSR20_SWIRQ2 0x00000400 /* SWIRQ2 interrupt 10 */
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#define CSR20_SWIRQ1 0x00000200 /* SWIRQ1 interrupt 9 */
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#define CSR20_SWIRQ0 0x00000100 /* SWIRQ0 interrupt 8 */
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#define CSR20_VMIRQ7 0x00000080 /* VMIRQ7 interrupt 7 */
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#define CSR20_VMIRQ6 0x00000040 /* VMIRQ7 interrupt 6 */
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#define CSR20_VMIRQ5 0x00000020 /* VMIRQ7 interrupt 5 */
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#define CSR20_VMIRQ4 0x00000010 /* VMIRQ4 interrupt 4 */
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#define CSR20_VMIRQ3 0x00000008 /* VMIRQ3 interrupt 3 */
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#define CSR20_VMIRQ2 0x00000004 /* VMIRQ2 interrupt 2 */
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#define CSR20_VMIRQ1 0x00000002 /* VMIRQ1 interrupt 1 */
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/*************************************************************************
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* CSR21 0x14 0x50 interrupt enable *
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*************************************************************************/
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#define CSR21_ACFIEN 0x80000000 /* ACFAIL interrupt 31 */
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#define CSR21_ABTIEN 0x40000000 /* ABORT interrupt 30 */
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#define CSR21_SFIEN 0x20000000 /* SYSFAIL interrupt 29 */
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#define CSR21_BERIEN 0x10000000 /* BERR interrupt 28 */
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#define CSR21_IAKIEN 0x08000000 /* IAK interrupt 27 */
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#define CSR21_SRQIEN 0x04000000 /* SRQ interrupt 26 */
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#define CSR21_SAKIEN 0x02000000 /* SAKF interrupt 25 */
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#define CSR21_GP7IEN 0x00800000 /* GP7 interrupt 23 */
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#define CSR21_DMAIEN 0x00400000 /* DMA interrupt 22 */
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#define CSR21_TT1IEN 0x00200000 /* TT1 interrupt 21 */
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#define CSR21_TT0IEN 0x00100000 /* TT0 interrupt 20 */
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#define CSR21_GP3IEN 0x00080000 /* GP3 interrupt 19 */
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#define CSR21_GP2IEN 0x00040000 /* GP2 interrupt 18 */
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#define CSR21_GP1IEN 0x00020000 /* GP1 interrupt 17 */
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#define CSR21_GP0IEN 0x00010000 /* GP0 interrupt 16 */
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#define CSR21_SWIEN7 0x00008000 /* SWIRQ7 interrupt 15 */
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#define CSR21_SWIEN6 0x00004000 /* SWIRQ6 interrupt 14 */
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#define CSR21_SWIEN5 0x00002000 /* SWIRQ5 interrupt 13 */
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#define CSR21_SWIEN4 0x00001000 /* SWIRQ4 interrupt 12 */
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#define CSR21_SWIEN3 0x00000800 /* SWIRQ3 interrupt 11 */
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#define CSR21_SWIEN2 0x00000400 /* SWIRQ2 interrupt 10 */
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#define CSR21_SWIEN1 0x00000200 /* SWIRQ1 interrupt 9 */
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#define CSR21_SWIEN0 0x00000100 /* SWIRQ0 interrupt 8 */
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#define CSR21_VMIEN7 0x00000080 /* VMIRQ7 interrupt 7 */
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#define CSR21_VMIEN6 0x00000040 /* VMIRQ7 interrupt 6 */
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#define CSR21_VMIEN5 0x00000020 /* VMIRQ7 interrupt 5 */
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#define CSR21_VMIEN4 0x00000010 /* VMIRQ4 interrupt 4 */
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#define CSR21_VMIEN3 0x00000008 /* VMIRQ3 interrupt 3 */
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#define CSR21_VMIEN2 0x00000004 /* VMIRQ2 interrupt 2 */
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#define CSR21_VMIEN1 0x00000002 /* VMIRQ1 interrupt 1 */
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/*************************************************************************
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* CSR23 0x16 0x5c interrupt clear *
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*************************************************************************/
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#define CSR23_ACFICL 0x80000000 /* ACFAIL clear 31 */
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#define CSR23_ABTICL 0x40000000 /* ABORT clear 30 */
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#define CSR23_SFICL 0x20000000 /* SYSFAIL clear 29 */
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#define CSR23_IAKICL 0x08000000 /* IAK clear 27 */
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#define CSR23_SRQICL 0x04000000 /* SRQ clear 26 */
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#define CSR23_SAKICL 0x02000000 /* SAK clear 25 */
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#define CSR23_DMAICL 0x00400000 /* DMA clear 22 */
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#define CSR23_TT1ICL 0x00200000 /* TT1 clear 21 */
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#define CSR23_TT0ICL 0x00100000 /* TT0 clear 20 */
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/*************************************************************************
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* IFR0 0x1c 0x70 interface register 0 *
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*************************************************************************/
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#define IFR0_SRQF 0x80000000 /* SRQ clear 31 */
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/*************************************************************************
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* IFR1 0x1d 0x74 interface register 1 *
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*************************************************************************/
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#define IFR1_SAKF 0x80000000 /* SAK clear 31 */
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/*************************************************************************
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* IFR3 0x1f 0x7c interface register 3 *
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*************************************************************************/
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#define IFR3_SWREN 0x80000000 /* software reset enable bit 31 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* INCdga001Vmeh */
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