95 lines
3.4 KiB
C
95 lines
3.4 KiB
C
/* msi.h - Message Signaled Interrupts header file */
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/*
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* Copyright (c) 2005, 2013 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01b,12jan13,j_z add MSI-X register.(WIND00333514)
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01a,24jun05,mdo Written.
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*/
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#ifndef msi_H
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#define msi_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* MSI-X registers */
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#define PCI_MSIX_CTL 0x02 /* Offset of MSI-X control register */
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#define PCI_MSIX_CTL_TABLE_SIZE 0x7ff
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#define PCI_MSIX_CTL_FUNCTION_MASK 0x4000
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#define PCI_MSIX_CTL_ENABLE 0x8000 /* MSI-X enable */
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#define PCI_MSIX_TABLE 0x04
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#define PCI_MSIX_TABLE_OFFSET_MASK 0xfffffff8
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#define PCI_MSIX_TABLE_BIR_MASK 0x07
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#define PCI_MSIX_PBA 0x08
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#define PCI_MSIX_PBA_OFFSET_MASK 0xfffffff8
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#define PCI_MSIX_PBA_BIR_MASK 0x07
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/* MSI-X Table Entry Dword offset */
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#define PCI_MSIX_MSG_ADDR_LOW 0x00
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#define PCI_MSIX_MSG_ADDR_HIGH 0x01
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#define PCI_MSIX_MSG_DATA 0x02
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#define PCI_MSIX_MSG_CTRL 0x03
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#define PCI_MSIX_MSG_CTRL_MASK (1 << 0)
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/* Message Signaled Interrupts registers */
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/* Message Control Register */
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#define PCI_MSI_CTL 0x02 /* Offset of MSI control register */
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#define PCI_MSI_CTL_ENABLE 0x01 /* MSI enable */
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#define PCI_MSI_CTL_MSG_ALLOC 0x70 /* Number of Messages allocated */
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#define PCI_MSI_CTL_MSG_MAX 0x0E /* Maximum Messages Allowed */
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#define PCI_MSI_CTL_64BIT 0x80 /* 64-bit addresses allowed */
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#define PCI_MSI_CTL_MASK 0x100 /* Per-vector masking capable */
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/* Message Address Register */
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#define PCI_MSI_ADDR_LO 0x04 /* Offset of MSI Address Lower 32 bits */
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/* Used for 32-bit MSI */
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#define PCI_MSI_ADDR_HI 0x08 /* Offset of MSI Address Upper 32 bits */
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/* Used with 64-bit MSI */
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/* Message Data Register */
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#define PCI_MSI_DATA_32 0x08 /* Offset of MSI Data Register */
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/* Used for 32-bit MSI */
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#define PCI_MSI_DATA_64 0x0C /* Offset of MSI Data Register */
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/* Used for 64-bit MSI */
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/* Message Per-Vector Mask Register */
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#define PCI_MSI_MASK_32 0x0C /* Offset of MSI Mask Register */
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/* Used for 32-bit MSI */
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#define PCI_MSI_MASK_64 0x10 /* Offset of MSI Mask Register */
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/* Used for 64-bit MSI */
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#define MSI_ENABLED (ctlReg) (ctlReg & PCI_MSI_CTL_ENABLE)
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#define ADDR_64BIT (ctlReg) (ctlReg & PCI_MSI_CTL_64BIT)
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#define MSI_ENABLE_MSG (ctlReg, msgNum) \
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ctlReg |= (((msgNum >> 1) << 4) & PCI_MSI_CTL_MESS_ALLOC);
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#define MSI_ENABLE (ctlReg, msgNum) MSI_ENABLE_MSG (ctlReg, msgNum); \
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ctlReg |= PCI_MSI_FLAGS_ENABLE
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#define MSI_DISABLE (ctlReg) ctlReg &= ~PCI_MSI_CTL_ENABLE
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#ifdef __cplusplus
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}
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#endif
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/* Used for 64-bit MSI */
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#endif /* msi_H */
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