654 lines
21 KiB
C
654 lines
21 KiB
C
/* amd8111LanEnd.h - END style AMD 8111 LAN PCI Ethernet driver header */
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/*
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* Copyright (c) 1998-2005, 2010 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01c,29apr10,pad Moved extern C statement after include statements.
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01b,01sep05,gtf modified for AMD8111 LAN END driver.
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01a,07dec98,snk added support 7997x[012] across architectures.
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written from 01b of lnPciEnd.h
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*/
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#ifndef __INCamd8111LanEndh
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#define __INCamd8111LanEndh
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#ifndef _ASMLANGUAGE
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#include <end.h>
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#include <cacheLib.h>
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#include <netinet/if_ether.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* board level/bus specific and architecture specific macros */
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#if (CPU_FAMILY == PPC)
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#ifndef AMD_LONG_WR
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#define AMD_LONG_WR(addr, value) (sysOutLong ((ULONG) addr, (ULONG) value))
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#endif
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#ifndef AMD_WORD_WR
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#define AMD_WORD_WR(addr, value) (sysOutWord ((ULONG) addr, (USHORT) value))
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#endif
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#ifndef AMD_BYTE_WR
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#define AMD_BYTE_WR(addr, value) (sysOutByte ((ULONG) addr, (UCHAR) value))
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#endif
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#ifndef AMD_LONG_RD
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#define AMD_LONG_RD(addr, value) (value = sysInLong ((ULONG) addr))
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#endif
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#ifndef AMD_WORD_RD
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#define AMD_WORD_RD(addr, value) (value = sysInWord ((ULONG) addr))
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#endif
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#ifndef AMD_BYTE_RD
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#define AMD_BYTE_RD(addr, value) (value = sysInByte ((ULONG) addr))
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#endif
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#endif /* CPU_FAMILY == PPC */
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#ifndef AMD_LONG_WR
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#define AMD_LONG_WR(addr, value) \
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(* (volatile UINT32 *) (addr) = ((UINT32) AMD_SWAP_LONG (value) ))
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#endif /* FEI_LONG_WR */
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#ifndef AMD_WORD_WR
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#define AMD_WORD_WR(addr, value) \
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(* (volatile UINT16 *) (addr) = ((UINT16) AMD_SWAP_WORD (value) ))
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#endif /* FEI_WORD_WR */
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#ifndef AMD_BYTE_WR
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#define AMD_BYTE_WR(addr, value) \
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(* (volatile UINT8 *) (addr) = (UINT8) (value) )
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#endif /* FEI_BYTE_WR */
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#ifndef AMD_LONG_RD
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#define AMD_LONG_RD(addr, value) \
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do { \
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UINT32 _temp_ = *(volatile UINT32 *)(addr); \
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(value) = (UINT32) AMD_SWAP_LONG (_temp_); \
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} while (0)
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#endif /* FEI_LONG_RD */
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#ifndef AMD_WORD_RD
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#define AMD_WORD_RD(addr, value) \
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do { \
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UINT16 _temp_ = *(volatile UINT16 *)(addr); \
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(value) = (UINT16) AMD_SWAP_WORD (_temp_); \
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} while (0)
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#endif /* FEI_WORD_RD */
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#ifndef AMD_BYTE_RD
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#define AMD_BYTE_RD(addr, value) \
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do { \
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(value) = (UINT8) (*(volatile UINT8 *)(addr)); \
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} while (0)
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#endif /* FEI_BYTE_RD */
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#if _BYTE_ORDER==_BIG_ENDIAN
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# define PCI_SWAP(x) ((amd8111LanBusEndianess) ? (int)(x) : LONGSWAP((int)(x)))
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#else
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# define PCI_SWAP(x) (x)
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#endif
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/* 32-bits */
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#define CHIPID (0x004)
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#define AUTO_POLL_VAL (0x098)
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/* 16-bites */
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#define AP0 (0x088)
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#define AP0_PHY0_ADDR_MASK 0x001f
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#define AP1 (0x08a)
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#define AP1_REG1_EN 0x8000
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#define AP1_REG1_ADDR_MASK 0x1f00
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#define AP1_PRE_SUP1 0x0040
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#define AP1_PHY1_DFLT 0x0020
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#define AP1_PHY1_ADDR_MASK 0x001f
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#define AP2 (0x08c)
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#define AP3 (0x08e)
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#define AP4 (0x090)
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#define AP5 (0x092)
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/* 32-bits */
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#define BADR (0x120)
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#define BADX0 (0x100)
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#define BADX1 (0x108)
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#define BADX2 (0x110)
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#define BADX3 (0x118)
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#define CMD0 (0x048)
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#define CMD0_RDMD0 0x00010000
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#define CMD0_TDMD3 0x00000800
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#define CMD0_TDMD2 0x00000400
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#define CMD0_TDMD1 0x00000200
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#define CMD0_TDMD0 0x00000100
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#define CMD0_UINTCMD 0x00000040
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#define CMD0_RX_FAST_SPND 0x00000020
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#define CMD0_TX_FAST_SPND 0x00000010
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#define CMD0_RX_SPND 0x00000008
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#define CMD0_TX_SPND 0x00000004
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#define CMD0_INTREN 0x00000002
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#define CMD0_RUN 0x00000001
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#define CMD2 (0x050)
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#define CMD2_CONDUIT_MODE 0x20000000
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#define CMD2_RPA 0x00100000
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#define CMD2_DRCVPA 0x00080000
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#define CMD2_DRCVBC 0x00040000
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#define CMD2_PROM 0x00020000
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#define CMD2_ASTRIP_RCV 0x00002000
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#define CMD2_RCV_DROP0 0x00001000
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#define CMD2_EMBA 0x00000800
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#define CMD2_DXMT2PD 0x00000400
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#define CMD2_LTINTEN 0x00000200
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#define CMD2_DXMTFCS 0x00000100
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#define CMD2_APAD_XMT 0x00000040
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#define CMD2_DRTY 0x00000020
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#define CMD2_INLOOP 0x00000010
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#define CMD2_EXLOOP 0x00000008
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#define CMD2_REXUFLO 0x00000002
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#define CMD3 (0x054)
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#define CMD3_JUMBO 0x00400000
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#define CMD3_VSIZE 0x00200000
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#define CMD3_VLONLY 0x00100000
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#define CMD3_VL_TAG_DEL 0x00080000
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#define CMD3_EN_PMGR 0x00004000
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#define CMD3_FORCE_FULL_DUPLEX 0x00001000
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#define CMD3_FORCE_LINK_STATUS 0x00000800
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#define CMD3_APEP 0x00000400
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#define CMD3_MPPLBA 0x00000200
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#define CMD3_BKPRS_EN 0x00000100
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#define CMD3_RESET_PHY_PULSE 0x00000004
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#define CMD3_RESET_PHY 0x00000002
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#define CMD3_PHY_RST_POL 0x00000001
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#define CMD7 (0x064)
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#define CMD7_PMAT_SAVE_MATCH 0x00000010
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#define CMD7_PMAT_MODE 0x00000008
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#define CMD7_MPEN_SW 0x00000002
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#define CMD7_LCMODE_SW 0x00000001
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#define CTRL1 (0x06c)
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#define CTRL1_RESET_PHY_WIDTH_MASK 0x001f0000
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#define CTRL1_XMTSP_MASK 0x00000300
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#define CTRL1_CACHE_ALIGN 0x00000010
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#define CTRL1_BURST_LIMIT_MASK 0x0000000f
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#define CTRL2 (0x070)
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#define CTRL2_FMDC_MASK 0x00000300
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#define CTRL2_XPHYRST 0x00000080
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#define CTRL2_XPHYANE 0x00000040
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#define CTRL2_XPHYFD 0x00000020
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#define CTRL2_XPHYSP_MASK 0x00000018
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#define CTRL2_APDW_MASK 0x00000007
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#define DLY_INT_A (0x0a8)
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#define DLY_INT_B (0x0ac)
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#define FLOW (0x0c8)
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/* 8-bits */
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#define IPG (0x18d)
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#define IFS1 (0x18c)
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/* 32-bits */
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#define INT0 (0x038)
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#define INT0_INTR 0x80000000
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#define INT0_INTPN 0x40000000
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#define INT0_LCINT 0x08000000
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#define INT0_APINT5 0x04000000
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#define INT0_APINT4 0x02000000
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#define INT0_APINT3 0x01000000
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#define INT0_APINT2 0x00800000
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#define INT0_APINT1 0x00400000
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#define INT0_APINT0 0x00200000
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#define INT0_MIIPDINT 0x00100000
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#define INT0_MCCINT 0x00020000
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#define INT0_MREINT 0x00010000
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#define INT0_SPNDINT 0x00004000
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#define INT0_MPINT 0x00002000
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#define INT0_TINT3 0x00000800
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#define INT0_TINT2 0x00000400
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#define INT0_TINT1 0x00000200
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#define INT0_TINT0 0x00000100
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#define INT0_UINT 0x00000080
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#define INT0_STINT 0x00000010
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#define INT0_RINT0 0x00000001
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#define INTEN0 (0x040)
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#define INTEN0_LCINTEN 0x08000000
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#define INTEN0_APINT5EN 0x04000000
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#define INTEN0_APINT4EN 0x02000000
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#define INTEN0_APINT3EN 0x01000000
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#define INTEN0_APINT2EN 0x00400000
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#define INTEN0_APINT1EN 0x00200000
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#define INTEN0_APINT0EN 0x00100000
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#define INTEN0_MIIPDINTEN 0x00080000
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#define INTEN0_MCCINTEN 0x00020000
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#define INTEN0_MREINTEN 0x00010000
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#define INTEN0_SPNDINTEN 0x00004000
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#define INTEN0_MPNINTEN 0x00002000
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#define INTEN0_TINTEN3 0x00000800
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#define INTEN0_TINTEN2 0x00000400
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#define INTEN0_TINTEN1 0x00000200
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#define INTEN0_TINTEN0 0x00000100
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#define INTEN0_STINTEN 0x00000010
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#define INTEN0_RINTEN0 0x00000001
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/* 64-bits */
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#define LADRF_L (0x168)
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#define LADRF_H (0x16c)
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/* 16-bits */
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#define MIB_ADRS (0x014)
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#define MIB_CMD_ACTIVE 0x8000
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#define MIB_RD_CMD 0x2000
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#define MIB_CLEAR 0x1000
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#define MIB_ADDRESS_MASK 0x001f
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/* 32-bits */
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#define MIB_DATA (0x010)
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/* 48-bits */
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#define MAC_ADRS (0x160)
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/* 32-bits */
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#define PHY_ACCESS (0x0d0)
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/* 32-bits */
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#define ON_NOW_PTRN0 (0x190)
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#define ON_NOW_PTRN1 (0x194)
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/* 16-bits */
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#define RCV_RING_LEN (0x150)
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/* 16-bits */
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#define SRAM_BND (0x17a)
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#define SRAM_BND_DEFAULT 0x08
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#define SRAM_SIZE (0x178)
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#define SRAM_SIZE_DEFAULT 0x10
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/* 32-bits */
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#define STAT0 (0x030)
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#define STAT0_PMAT_DET 0x00010000
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#define STAT0_MP_DET 0x00008000
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#define STAT0_LC_DET 0x00004000
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#define STAT0_SPEED_MASK 0x00000380
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#define STAT0_FULL_DUPLEX 0x00000040
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#define STAT0_LINK_STATUS 0x00000020
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#define STAT0_AUTONEG_COMPLETE 0x00000010
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#define STAT0_MIIPD 0x00000008
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#define STAT0_RX_SUSPENDED 0x00000004
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#define STAT0_TX_SUSPENDED 0x00000002
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#define STAT0_RUNNING 0x00000001
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/* 16-bits */
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#define STVAL (0x0d8)
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/* 16-bits */
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#define XMT_RING0_LEN (0x140)
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#define XMT_RING1_LEN (0x144)
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#define XMT_RING2_LEN (0x148)
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#define XMT_RING3_LEN (0x14c)
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/* 32-bits */
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#define XMT_RING_LIMIT (0x07c)
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/* Bit Fields */
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typedef struct rxDesc
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{
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UINT32 RD[4] ;
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} AMD_RD ;
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typedef struct txDesc
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{
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UINT32 TD[4] ;
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} AMD_TD ;
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#define RD_USER_SPACE 0
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#define RD_WORD1 1
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#define RD_MCNT 1
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#define RD_WORD2 2
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#define RD_BCNT 2
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#define RD_FLAGS 2
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#define RD_RBADR 3
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/* Word 0x8 */
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#define RD_OWN 0x80000000
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#define RD_ERR 0x40000000
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#define RD_FRAM 0x20000000
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#define RD_OFLO 0x10000000
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#define RD_CRC 0x08000000
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#define RD_BUFF 0x04000000
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#define RD_STP 0x02000000
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#define RD_ENP 0x01000000
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#define RD_PAM 0x00400000
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#define RD_LAFM 0x00200000
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#define RD_BAM 0x00100000
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#define RD_TT_MASK 0x000c0000
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#define RD_BCNT_MASK 0x0000ffff
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#define TD_WORD0 0
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#define TD_BCNT 0
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#define TD_FLAGS 0
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#define TD_WORD1 1
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#define TD_TCC 1
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#define TD_TCI 1
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#define TD_TBADR 2
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#define TD_USER_SPACE 3
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/* Word 0x0 */
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#define TD_OWN 0x80000000
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#define TD_ADD_FCS 0x20000000
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#define TD_LTINT 0x10000000
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#define TD_PRI_LOCK 0x04000000
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#define TD_STP 0x02000000
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#define TD_ENP 0x01000000
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#define TD_KILL 0x00400000
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#define TD_BCNT_MASK 0x0000ffff
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/* Word 0x4 */
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#define TD_TCC_MASK 0x00030000
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#define TD_TCI_MASK 0x0000ffff
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/* Control block definitions for AMD PCnet (Ethernet) chip. */
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typedef union addrFilter /* logical address filter layout */
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{
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UINT8 lafBytes [8]; /* (8) bytes */
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UINT16 lafWords [4]; /* (4) 16-bit words */
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UINT32 lafDwords [2]; /* (2) 32-bit dwords */
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} ADDR_FILTER;
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typedef enum filterModCmd /* addrFilterMod() commands */
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{
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AMD_LADRF_ADD, /* add a logical address */
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AMD_LADRF_DEL, /* delete a logical address */
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AMD_LADRF_ADD_ALL, /* add all logical addresses */
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AMD_LADRF_DEL_ALL /* delete all logical addresses */
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} FILTER_MOD_CMD;
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/* CRC for logical address filter */
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#define AMD_CRC_POLYNOMIAL (0xedb88320) /* Ethernet CRC polynomial */
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#define AMD_CRC_TO_LAF_IX(crc) ((crc) >> 26) /* get 6 MSBits */
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#define AMD_LAF_LEN (8) /* logical addr filter length */
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#define AMD_LA_LEN (6) /* logical address length */
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#define BITS_PER_LA (8 * AMD_LA_LEN) /* logical addr length bits */
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/* Definitions for the drvCtrl specific flags field */
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#define LS_PROMISCUOUS_FLAG 0x1 /* set the promiscuous mode */
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#define LS_MEM_ALLOC_FLAG 0x2 /* allocating memory flag */
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#define LS_PAD_USED_FLAG 0x4 /* padding used flag */
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#define LS_RCV_HANDLING_FLAG 0x8 /* handling recv packet */
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#define LS_START_OUTPUT_FLAG 0x10 /* trigger output flag */
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#define LS_POLLING 0x20 /* polling flag */
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#define LS_MODE_MEM_IO_MAP 0x100 /* device registers memory mapped */
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#define LS_MODE_DWIO 0x200 /* device in 32 bit mode */
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#define LS_MODE_NOSWAP_MASTER 0x400 /* don't swap PCI master I/O ops */
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/* descriptor size */
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#define RD_SIZ sizeof(AMD_RD)
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#define TD_SIZ sizeof(AMD_TD)
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/* How much work we're allowed to do in the RX handler (# of pkts processed) */
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#define AMD_RX_LIMIT 32
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/* How many descriptors we want to use up in a single gather-write transmit */
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#define AMD_MAX_FRAGS 32
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/* */
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typedef struct amd8111LanBoardInfoType
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{
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UINT32 vector; /* interrupt vector number */
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UINT32 baseAddr; /* memory base address for CSR */
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UINT32 pciMemAddr ; /* PCI memory base address from CPU */
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UCHAR enetAddr[6]; /* ethernet address */
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int (*intEnable)(int unit); /* board specific interrupt enable routine */
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int (*intDisable)(int unit); /* board specific interrupt disable routine */
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int (*intAck) (int unit); /* interrupt ack */
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STATUS (*intConnect) (VOIDFUNCPTR * vector, VOIDFUNCPTR routine, int parameter);
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STATUS (*intDisconnect) (VOIDFUNCPTR * vector, VOIDFUNCPTR routine, int parameter);
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UINT32 (*sysLocalToBus)(int unit,UINT32 localAdr);
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UINT32 (*sysBusToLocal)(int unit,UINT32 sysAdr);
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/* configuration parameters, user can override in the BSP */
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UINT8 phyAddr; /* PHY device address, valid addresses: 0-32 */
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UINT8 phySpeed;
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UINT8 phyDpx;
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UINT8 fill0;
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} AMD8111_LAN_BOARD_INFO ;
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/* The definition of the driver control structure */
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typedef struct amd8111LanDevice
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{
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END_OBJ endObj; /* The class we inherit from */
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int unit; /* unit number of the device */
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int rdNum ; /* total number of RDs */
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int rdIndex; /* current RD send index */
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int rringSize; /* RD ring size */
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int rringLen; /* RD ring length (bytes) */
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volatile AMD_RD * pRring; /* RD ring start */
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int tdNum ; /* total number of TDs */
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int tdIndex; /* current TD transmit index */
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int tdIndexC; /* current TD cleaning index */
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int tringSize; /* TD ring size */
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int tringLen; /* TD ring length (bytes) */
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volatile AMD_TD * pTring; /* TD ring start */
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int inum; /* interrupt number */
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int ilevel; /* interrupt level */
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volatile char * pShMem; /* real ptr to shared memory */
|
|
volatile char * pShMemEnd; /* real ptr to shared memory end */
|
|
volatile char * memBase; /* PCnet memory pool base */
|
|
volatile char * memAdrs; /* PCnet memory pool base */
|
|
|
|
UINT32 shMemPtoVOffset; /* bias to convert pShMem P->V */
|
|
|
|
UINT32 devAdrs; /* device structure address */
|
|
|
|
UINT32 chipId; /* (csr88|csr89) chip ID value */
|
|
int memSize; /* PCnet memory pool size */
|
|
int memWidth; /* width of data port */
|
|
int offset; /* offset of data in the buffer */
|
|
volatile UINT32 flags; /* Our local flags */
|
|
UINT32 pciMemBase; /* memory base as seen from PCI*/
|
|
UINT8 enetAddr[6]; /* ethernet address */
|
|
CACHE_FUNCS cacheFuncs; /* cache function pointers */
|
|
|
|
volatile BOOL txBlocked; /* transmit flow control */
|
|
volatile BOOL txCleaning; /* transmit descriptor cleaning */
|
|
|
|
CL_POOL_ID pClPoolId; /* cluster pool Id */
|
|
M_CL_CONFIG mClCfg; /* mBlk & cluster config structure */
|
|
CL_DESC clDesc; /* cluster descriptor table */
|
|
|
|
END_ERR lastError; /* Last error passed to muxError */
|
|
volatile BOOL errorHandling; /* task level error handling */
|
|
|
|
M_BLK_ID * mBlks; /* saved mBlk pointers */
|
|
|
|
AMD8111_LAN_BOARD_INFO board ;
|
|
|
|
/* Hold current values of these registers */
|
|
|
|
UINT32 cmd0 ;
|
|
UINT32 cmd2 ;
|
|
UINT32 cmd3 ;
|
|
UINT32 cmd7 ;
|
|
UINT32 inten0 ;
|
|
|
|
} AMD8111_LAN_DRV_CTRL;
|
|
|
|
/*
|
|
* MIB statistics. The variable positions correspond the the index position
|
|
* required to access the given value. For example, rxvMissPkts is index 0,
|
|
* rcvOctets is index 1 and so on.
|
|
*/
|
|
|
|
typedef struct amd8111LanStatCounterType {
|
|
UINT32 rcvMissPkts ; /* 0x0 */
|
|
UINT32 rcvOctets ;
|
|
UINT32 rcvBroadCastPkts ;
|
|
UINT32 rcvMultiCastPkts ;
|
|
UINT32 rcvUndersizePkts ;
|
|
UINT32 rcvOversizePkts ;
|
|
UINT32 rcvFragments ;
|
|
UINT32 rcvJabbers ;
|
|
UINT32 rcvUnicastPkts ;
|
|
UINT32 rcvAlignmentErrors ;
|
|
UINT32 rcvFCSErrors ;
|
|
UINT32 rcvGoodOctets ;
|
|
UINT32 rcvMACCtrl ;
|
|
UINT32 rcvFlowCtrl ;
|
|
UINT32 rcvPkts64Octets ;
|
|
UINT32 rcvPkts65to127Octets ;
|
|
UINT32 rcvPkts128to255ctets ; /* 0x10 */
|
|
UINT32 rcvPkts256to511ctets ;
|
|
UINT32 rcvPkts512to1023ctets ;
|
|
UINT32 rcvPkts1024to1518ctets ;
|
|
UINT32 rcvUnsupportedOpcode ;
|
|
UINT32 rcvSymbolErrors ;
|
|
UINT32 rcvDropPktsRing0 ;
|
|
UINT32 reserved0[3] ;
|
|
UINT32 rcvJumboPkts ;
|
|
UINT32 reserved1[5] ;
|
|
UINT32 xmtUnderrunPkts ; /* 0x20 */
|
|
UINT32 xmtOctets ;
|
|
UINT32 xmtPackets ;
|
|
UINT32 xmtBroadCastPkts ;
|
|
UINT32 xmtMultiCastPkts ;
|
|
UINT32 xmtCollisions ;
|
|
UINT32 xmtUnicastPkts ;
|
|
UINT32 xmtOneCollision ;
|
|
UINT32 xmtMultipleCollision ;
|
|
UINT32 xmtDeferredTransmit ;
|
|
UINT32 xmtLateCollision ;
|
|
UINT32 xmtExcessiveDefer ;
|
|
UINT32 xmtLossCarrier ;
|
|
UINT32 xmtExcessiveCollision ;
|
|
UINT32 xmtBackPressure ;
|
|
UINT32 xmtFlowCtrl ;
|
|
UINT32 xmtPkts64Octets ; /* 0x30 */
|
|
UINT32 xmtPkts65to127Octets ;
|
|
UINT32 xmtPkts128to255Octets ;
|
|
UINT32 xmtPkts256to511Octets ;
|
|
UINT32 xmtPkts512to1023Octets ;
|
|
UINT32 xmtPkts1024to1518Octets ;
|
|
UINT32 xmtOversizePkts ;
|
|
UINT32 xmtJumboPkts ; /* 0x37 */
|
|
|
|
} AMD8111_LAN_STAT_COUNTER ;
|
|
|
|
/* Configuration items */
|
|
|
|
#define AMD_MIN_FBUF (100) /* Min sizeof first buffer in chain */
|
|
|
|
#define AMD_BUFSIZ (ETHERMTU + SIZEOF_ETHERHEADER + 6)
|
|
|
|
#define AMD_SPEED (10000000)
|
|
|
|
#define AMD_RD_RLEN (7) /* ring size as a ^ 2 => 128 RD's */
|
|
#define AMD_TD_TLEN (7) /* ring size as a ^ 2 => 128 TD's */
|
|
|
|
#define AMD_RD_MIN (2) /* min descriptors 4 */
|
|
#define AMD_TD_MIN (2) /* min descriptors 4 */
|
|
|
|
#define AMD_RD_MAX (9) /* max descriptors 512 */
|
|
#define AMD_TD_MAX (9) /* max descriptors 512 */
|
|
|
|
#define AMD8111_LAN_DEV_NAME "amdPci" /* name of the device */
|
|
#define AMD8111_LAN_DEV_NAME_LEN (7) /* length of the name string */
|
|
#define AMD8111_LAN_APROM_SIZE (32) /* hardware Address PROM size bytes */
|
|
|
|
#define AMD_LITTLE_ENDIAN (0) /* little endian PCI bus */
|
|
#define AMD_BIG_ENDIAN (1) /* big endian PCI bus */
|
|
#define AMD_ACTIVE_LOW (0) /* active-low interrupt line */
|
|
#define AMD_ACTIVE_HI (1) /* active-high interrupt line */
|
|
|
|
#define AMD_RD_OWNED(rd) ( PCI_SWAP ((rd)->RD [RD_FLAGS]) & RD_OWN )
|
|
#define AMD_TD_OWNED(td) ( PCI_SWAP ((td)->TD [TD_FLAGS]) & TD_OWN )
|
|
|
|
#define AMD_PKT_LEN_GET(rd) ( PCI_SWAP ((rd)->RD [RD_MCNT]) & RD_BCNT_MASK )
|
|
|
|
#if defined(__STDC__) || defined(__cplusplus)
|
|
|
|
IMPORT STATUS amd8111LanInitParse (AMD8111_LAN_DRV_CTRL * pDrvCtrl, char * initString);
|
|
IMPORT END_OBJ * amd8111LanEndLoad (char * initString);
|
|
|
|
#else
|
|
|
|
IMPORT STATUS amd8111LanInitParse ();
|
|
IMPORT END_OBJ * amd8111LanEndLoad ();
|
|
|
|
#endif /* __STDC__ */
|
|
|
|
#endif /* _ASMLANGUAGE */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __INCamd8111LanEndh */
|