398 lines
11 KiB
C
398 lines
11 KiB
C
/* archArm.h - ARM specific header */
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/*
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* Copyright (c) 1996, 1998, 1999, 2001, 2003-2011, 2013
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* Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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02t,01jun13,yjw update for ARMARCH7M
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02s,12aug11,jb WIND00238999 Limit Device Power Mgmt to ARMARCH7
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02r,17nov10,dbr define _WRS_ARCH_HAS_DEV_PWR_MGMT for device power management
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02q,16sep10,gls added VX_OBJ_ALIGN_SIZE
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02p,29jul10,pad Moved extern C statement after include statements.
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02o,27aug10,rlp Added _WRS_ARCH_HAS_VXDBG_BP_ADDR_CHECK macro.
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02n,24aug10,jdw Fix _WRS_REV_INSN_SET_CHANGE for Thumb2
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02m,09jun10,m_h Thumb-2 Support
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02l,10mar10,j_b define _WRS_PHYS_ADDR_IS_64_BITS for XScale, ARMv6+
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(WIND00129408)
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02k,20oct09,z_l add SMP support for ARMARCH7
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02j,25feb09,j_b merge ARM SMP support, incl adding VSB header file:
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22feb08,j_b replace intUnlock with intCpuUnlock
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12nov07,jmp Define _WRS_ARCH_HAS_VXDBG_CPU_CTRL_SUPPORT
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02nov07,jb Add coherency flag for SMP and build exclusions
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10oct07,j_b define _WRS_ARCH_HAS_DBG_IPI
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02i,27feb09,m_h ARMARCH7 Support
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02h,31jul08,tcr change macro for compatibility
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02g,19may08,tcr update SV instrumentation
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02f,16aug07,j_b added _WRS_MMU_HAS_MAP_STATE_API
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02e,08jun07,j_b Add definition for _WRS_VX_NO_GLOBAL_ERRNO
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02d,21may07,j_b define _WRS_ARCH_HAS_IDLE_TASK, VX_MAX_SMP_CPUS
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02c,04may07,zl updated portable library build configuration,
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added _WRS_CPU_HAS_CLZ_INSTR.
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02b,21feb07,jmg Added include vxPortableP.h
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02a,11dec06,kk removed references to _WRS_BASE6_SCHEDULER, no longer needed
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01z,21jun06,jb Re-enable fast ffs for arch5, make ARMARCH6 64 bit PHYS_ADDR
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01y,02mar06,jb Fix for SPR 118321 - vfp references in 920t
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01x,01feb06,jb Adding VFP Support
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01w,12jan06,jb Enabling 920t variant support
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01v,10jan06,hya Add ARM CPU variant code for FFS(x) (WRN)
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01u,19dec05,jb Changing XSCALE to 64 bit PHYS_ADDR
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01t,24aug05,h_k Added _WRS_SUPPORT_CACHE_XLATE.
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01s,12apr05,kk remove _WRS_OBJLIB_SUPPORT_VERIFY_TRAP macro (SPR# 106486)
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01r,28mar05,scm add _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
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01q,18feb05,dbt Moved some loader specific macros to elfArm.h.
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01p,17feb05,scm add _WRS_OSM_INIT definition, and clarify
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PORTABLE/NON-PORTABLE inclussion
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01o,17jan05,jb Adding architecture specific objVerify support
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01n,08sep04,scm move INSTR to archArmCommon.h
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01m,10aug04,scm undef "OPTIMIZE", define "PORTABLE"...
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01l,27apr04,cjj Defined workQLib_PORTABLE
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01k,01dec03,scm clean up, SPR #90358... remove obnoxious warning...
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01j,25nov03,pes Move setting of _BYTE_ORDER macro into archArmCommon.h
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01i,14nov03,job Moved some blib stuff to archArmCommon.h
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01h,13nov03,pes Add include of archArmCommon.h
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01h,29oct03,sn gcc 3.3.2 does not currently support arm or sh
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01g,27aug03,to added defines for semLib.
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01f,07may03,pes PAL conditional compilation cleanup. Phase 2.
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01e,29apr03,pes PAL conditional compilation cleanup.
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01d,13mar01,sn SPR 73723 - define supported toolchains
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01c,20jan99,cdp removed support for old ARM libraries.
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01b,17aug98,cdp added big-endian and multiple cachelib support.
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01a,08may96,cdp written based on archI86.h
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*/
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#ifndef __INCarchArmh
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#define __INCarchArmh
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#include <vsbConfig.h>
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/* In the cases where vxWorks.h is not defined first... */
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#if !defined (TRUE)
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#define TRUE 1
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#endif
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#if !defined (FALSE)
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#define FALSE 0
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#endif
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#undef _ARCH_SUPPORTS_GCC
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#define _ARCH_SUPPORTS_DCC
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/* define to indicate ARM supports device power management */
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#if (CPU==ARMARCH7) || (CPU==ARMARCH7_T2)
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#define _WRS_ARCH_HAS_DEV_PWR_MGMT
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#endif /* (CPU==ARMARCH7) || (CPU==ARMARCH7_T2) */
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/* temporary macro to indicate ARM uses the idle task stack */
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#define _WRS_ARCH_HAS_IDLE_TASK
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/* temporary define to indicate ARM uses task-specific errnos */
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#define _WRS_VX_NO_GLOBAL_ERRNO
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/* temporary define to indicate ARM supports MMU state info with map request */
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#define _WRS_MMU_HAS_MAP_STATE_API
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/* temporary macro to indicate ARM has Debug IPI */
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#define _WRS_ARCH_HAS_DBG_IPI
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/* indicates that ARM has VxDBG CPU control support */
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#define _WRS_ARCH_HAS_VXDBG_CPU_CTRL_SUPPORT
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/*
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* Indicate that the ARM architecture has the VxDBG support to check the
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* alignment of the breakpoint address.
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*/
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#define _WRS_ARCH_HAS_VXDBG_BP_ADDR_CHECK
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#undef VX_MAX_SMP_CPUS
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#define VX_MAX_SMP_CPUS 4 /* maximum processors in SMP configuration */
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/*
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* For SMP, any shared data region that is created from the RAM need
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* to be memory coherent.
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* So we need to set the page attribute to MMU_ATTR_CACHE_COHERENCY.
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* The arches, need to specify this via the macro
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* VM_DEFAULT_CACHE_COHERENCY_ATTR
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*/
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#ifdef _WRS_CONFIG_SMP
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/* Limit SMP build to ARMARCH6 and ARMARCH7 little endian */
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#if ((CPU == ARMARCH6) || (CPU == ARMARCH7)) && !defined(ARMEB) && !defined(__ARMEB__)
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#define VM_DEFAULT_CACHE_COHERENCY_ATTR MMU_ATTR_CACHE_COHERENCY
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#else
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#error SMP build is NOT supported by this architecture/tool combination
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#endif /* (CPU == ARMARCH6) && !defined(ARMEB) && !defined(__ARMEB__) */
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#endif /* _WRS_CONFIG_SMP */
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#define _DYNAMIC_BUS_SIZING FALSE /* require alignment for swap */
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#define _ARCH_MULTIPLE_CACHELIB TRUE /* multiple cache libraries */
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/* macros for AIM Cache */
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#define _WRS_SUPPORT_CACHE_XLATE /* cache virt-phys translate */
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#if !defined(ARMCPU920T)
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/* Say VFP is Supported */
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#define _WRS_HW_VFP_SUPPORT
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#endif /* !defined(ARMCPU920T) */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if ((CPU == XSCALE) || (CPU == ARMARCH6) || (CPU == ARMARCH7) \
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|| (CPU == ARMARCH7_T2))
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/* physical addresses are represented with 64 bits for these CPUs */
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#define _TYPE_PHYS_ADDR typedef UINT64 PHYS_ADDR
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#define _WRS_PHYS_ADDR_IS_64_BITS
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#endif /* ((CPU == XSCALE, ARMARCH6, ARMARCH7, ARMARCH7_T2)) */
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#ifdef __cplusplus
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}
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#endif
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#include "arm.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* PAL additions */
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/*
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* VX_OBJ_ALIGN_SIZE is the default allocation boundary for kernel objects.
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* This is used for both statically and dynamically allocated objects.
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*/
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#define VX_OBJ_ALIGN_SIZE 8 /* 8-byte alignment */
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/* moved here from h/private/eventP.h */
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/*
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* (Borrowed from PPC.)
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*
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* Macro for event logging of intEnt events for ARM architectures.
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* The ARM architecture is different in that there is only one external
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* interrupt line coming into the CPU. At the time of the intEnt, the
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* external interrupt number is unknown, meaning that logging cannot
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* take place at this time. In this architecture, the logging of an
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* intEnt event is deferred until the interrupt controller driver
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* is executed.
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* Since the logging has to take place in drivers and/or BSP world files,
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* the details of how the logging to be done has been deferred to a macro
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* which is defined here.
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*
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* Note: This replaces the previous technique of saving the timestamp
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* during the intEnt code to be used later, when the logging was done.
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* SPR 21868 refers to a problem in which this can give rise to out-of-order
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* timestamps in the event log.
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*/
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#define WV_EVT_INT_ENT(intNum) EVT_CTX_1(EVENT_INT_ENTER, intNum);
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/* moved here from h/private/classLibP.h */
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#define OBJ_CLASS_initRtn 0x24 /* Offsets into OBJ_CLASS */
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/* status codes */
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#define S_vmLib_NO_FREE_REGIONS (M_vmLib | 6)
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#define S_vmLib_ADDRS_NOT_EQUAL (M_vmLib | 7)
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/* from dbgLib.c */
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#define _WRS_FRAME_PRINT_STRING " : "
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/* from loadElfLib.c */
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#define _WRS_USE_ELF_LOAD_FORMAT
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/* from periodHost.c, repeatHost.c, shell.c, and taskLib.c */
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#if (ARM_THUMB) || (ARM_THUMB2)
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#define _WRS_CHANGE_INSN_SET_ENABLE
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#define _WRS_CHANGE_INSN_SET(p) (p) = ((FUNCPTR)(((UINT32)(p))|1))
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#define _WRS_CHANGE_INSN_SET_PTR(p) ((FUNCPTR)(((UINT32)(p))|1))
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#define _WRS_REV_INSN_SET_CHANGE(p) ((FUNCPTR)(((UINT32)(p)) & ~1))
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#endif /* ARM_THUMB || (ARM_THUMB2) */
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/* OSM support for stack protection, used in sysOsmLib.c */
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#define _WRS_OSM_INIT
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/* Interrupt stack protection, used in usrDepend.c and usrKernelStack.c */
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#define _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
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/*
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* if OSM support not available for stack protection,
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* then support can not be available for interrupt
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* stack protection.
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*/
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#if !defined(_WRS_OSM_INIT)
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#undef _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
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#endif
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#if defined(_ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK)
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#undef _WRS_SVC_INT_STACK
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#undef _WRS_IRQ_INT_STACK
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#undef _WRS_DUAL_INT_STACK
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#undef _WRS_SPLIT_STACKS
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#else
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/*
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* Old split interrupt stack method...,
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* not used when OSM stack protection is
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* enabled...
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*/
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/* from usrLib.c */
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#define _WRS_SVC_INT_STACK
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#define _WRS_IRQ_INT_STACK
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#define _WRS_DUAL_INT_STACK
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/* from kernelLib.c */
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/*
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* The ARM family uses 3 interrupt stacks. The ratio of the sizes of
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* these stacks is dependent on the interrupt structure of the board
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* and so is handled in the BSP code. Note that FIQ is now external to
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* VxWorks.
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*/
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#define _WRS_SPLIT_STACKS {if (_func_armIntStackSplit != NULL) \
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(_func_armIntStackSplit)(vxIntStackBase, intStackSize);}
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#endif /* _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK */
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/* from xdr_float.c */
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#define FLOAT_NORM
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/* Set to force the use of the big-endian call to XDR_GETLONG() */
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#define _WRS_XDR_FORCE_BE
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#define _WRS_ENABLE_IDLE_INTS {intCpuUnlock(0);}
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/* macros for getting frame and return PC from a jmp_buf */
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#define _WRS_FRAMEP_FROM_JMP_BUF(env) ((char *) (env)[0].reg.reg_sp)
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#define _WRS_RET_PC_FROM_JMP_BUF(env) ((INSTR *) (env)[0].reg.reg_pc)
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#ifdef __cplusplus
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}
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#endif
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#include <arch/arm/archArmCommon.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* variants that support the clz instruction, "count leading zeroes" */
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#if ((CPU == XSCALE) || (CPU == ARMARCH6) || (CPU == ARMARCH5) \
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|| (CPU == ARMARCH7) || (CPU == ARMARCH7_T2) || (CPU == ARMARCH7M))
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#define _WRS_CPU_HAS_CLZ_INSTR
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#endif /* CPU = XSCALE ... ARMARCH7_T2 */
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#ifndef _ASMLANGUAGE
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#ifdef _WRS_CPU_HAS_CLZ_INSTR
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/* optimize FFS(x) in network code for CPUs supporting clz instruction */
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#undef FFS
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#define FFS(x) (31 - _countLeadingZeroes(x))
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#if defined (__GNUC__)
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/*
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* Return the number of zero bits in bit positions more significant
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* than the first set bit.
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* We don't have to handle the x=0 case, this is only called
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* when x != 0. Returns a value y in the range 31 >= y >= 0.
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* 0 indicates the most significant bit.
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*/
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static __inline__ unsigned int _countLeadingZeroes
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(
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unsigned int x
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)
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{
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unsigned int y;
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__asm__ ("clz %0, %1"
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: "=r" (y)
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: "r" (x)
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);
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return y;
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}
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#elif defined (_DIAB_TOOL)
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#pragma pure_function _countLeadingZeroes
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__asm unsigned int _countLeadingZeroes
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(
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unsigned int x
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)
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{
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% reg x
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! "r0"
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clz r0, x
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}
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#else /* !_DIAB_TOOL */
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/* Unknown compiler, use default */
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#undef FFS
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#define FFS(x) (ffsMsb(x) - 1)
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#endif /* _DIAB_TOOL */
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#else /* _WRS_CPU_HAS_CLZ_INSTR */
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/* use default */
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#undef FFS
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#define FFS(x) (ffsMsb(x) - 1)
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#endif /* _WRS_CPU_HAS_CLZ_INSTR */
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#endif /* ! _ASMLANGUAGE */
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/* End PAL */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCarchArmh */
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