232 lines
8.9 KiB
C
232 lines
8.9 KiB
C
/* regsMips.h - MIPS registers */
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/*
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* Copyright (c) 1991-1993, 1996-1997, 2001, 2003,
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* 2006-2007, 2010-2011 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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* This file has been developed or significantly modified by the
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* MIPS Center of Excellence Dedicated Engineering Staff.
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* This notice is as per the MIPS Center of Excellence Master Partner
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* Agreement, do not remove this notice without checking first with
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* WR/Platforms MIPS Center of Excellence engineering management.
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*/
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/*
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modification history
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--------------------
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01u,25may11,slk Add extended interrupts for RMI _xlp variant
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01t,27may10,d_c Rename CAVIUM_CNMIPS_* to _WRS_CAVIUM_CNMIPS_* and define in
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arch Makefile
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01s,31mar10,d_c Add cav_cn5xxx and cav_cn6xxx variants
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01r,20sep07,d_c Add extended interrupts for RMI _xlr variant
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01q,10aug07,rlg MIPS library restructure changes
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01p,29jul07,pes Addition of more registers for Cavium save/restore
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01o,20sep06,pes Add declaration of WIND_CPU_STATE.
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01n,11sep03,jmt Modify Register Set for Base 6
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01m,22aug03,jmt Add MMU Support
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01l,16jul01,ros add CofE comment
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01k,30dec97,dbt added common names for registers
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01j,16jan96,mem added cause and fpcsr to REG_SET.
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01i,18oct93,cd added R4000 support.
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01h,22sep92,rrr added support for c++
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01g,09jul92,ajm added defines for ASMLANGUAGE signals
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01f,03jun92,ajm updated file name references to match real name
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01e,26may92,rrr the tree shuffle
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01d,12mar92,yao added SR_OFFSET, PC_OFFSET, GREG_BASE,GREG_OFFSET.
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01c,04oct91,rrr passed through the ansification filter
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-changed ASMLANGUAGE to _ASMLANGUAGE
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-changed copyright notice
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01b,27may91,ajm reordered REG_SET to mirror R3KESF
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01a,01apr91,ajm derived from 01d of 68K.
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*/
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#ifndef __INCregsMipsh
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#define __INCregsMipsh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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typedef struct /* REG_SET - MIPS architecture register set */
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{
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ULONG sr; /* process status register */
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INSTR *pc; /* program counter - really epc! */
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_RType lo; /* divide lo register */
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_RType hi; /* divide hi register */
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_RType gpreg[32]; /* data registers */
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/* cause & fpcsr are only set for wdb traps, from ESFMIPS */
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ULONG cause; /* cause reg for branch bit in getNpc() */
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ULONG fpcsr; /* fp cause reg for getNpc() */
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ULONG intCtrl; /* extended interrupt control */
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ULONG _ULextra1; /* extra */
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_RType tlbhi; /* current address space storage */
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_RType _RTextra2; /* extra */
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_RType _RTextra3; /* extra */
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_RType _RTextra4; /* extra */
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_RType _RTextra5; /* extra */
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_RType _RTextra6; /* extra */
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_RType _RTextra7; /* extra */
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_RType _RTextra8; /* extra */
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_RType _RTextra9; /* extra */
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_RType _RTextra10; /* extra */
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} REG_SET;
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#if defined(_WRS_CAVIUM_CNMIPS_CORE) || defined(_WRS_CAVIUM_CNMIPS_II_CORE)
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/* use "extra" registers for the multiplier context */
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#define regP0 _RTextra3
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#define regP1 _RTextra4
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#define regP2 _RTextra5
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#define regMPL0 _RTextra6
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#define regMPL1 _RTextra7
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#define regMPL2 _RTextra8
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#define regTlo _RTextra9
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#define regThi _RTextra10
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#endif /* defined(_WRS_CAVIUM_CNMIPS_CORE) || defined(_WRS_CAVIUM_CNMIPS_II_CORE) */
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#if defined(_WRS_MIPS_NETLOGIC_CPU)
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#define regEIMR _RTextra3
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#endif /* _WRS_MIPS_NETLOGIC_CPU */
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/* Used to describe the register state of a cpu. May ultimately be
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* replaced by using REG_SET directly if no other elements are needed */
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typedef struct wind_cpu_state
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{
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REG_SET regs;
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} WIND_CPU_STATE;
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/* some common names for registers */
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#define zeroReg gpreg[0] /* wired zero */
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#define atReg gpreg[1] /* assembler temp */
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#define v0Reg gpreg[2] /* function return 0 */
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#define v1Reg gpreg[3] /* function return 1 */
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#define a0Reg gpreg[4] /* parameter 0 */
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#define a1Reg gpreg[5] /* parameter 1 */
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#define a2Reg gpreg[6] /* parameter 2 */
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#define a3Reg gpreg[7] /* parameter 3 */
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#define t0Reg gpreg[8] /* caller saved 0 */
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#define t1Reg gpreg[9] /* caller saved 1 */
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#define t2Reg gpreg[10] /* caller saved 2 */
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#define t3Reg gpreg[11] /* caller saved 3 */
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#define t4Reg gpreg[12] /* caller saved 4 */
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#define t5Reg gpreg[13] /* caller saved 5 */
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#define t6Reg gpreg[14] /* caller saved 6 */
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#define t7Reg gpreg[15] /* caller saved 7 */
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#define s0Reg gpreg[16] /* callee saved 0 */
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#define s1Reg gpreg[17] /* callee saved 1 */
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#define s2Reg gpreg[18] /* callee saved 2 */
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#define s3Reg gpreg[19] /* callee saved 3 */
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#define s4Reg gpreg[20] /* callee saved 4 */
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#define s5Reg gpreg[21] /* callee saved 5 */
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#define s6Reg gpreg[22] /* callee saved 6 */
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#define s7Reg gpreg[23] /* callee saved 7 */
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#define t8Reg gpreg[24] /* caller saved 8 */
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#define t9Reg gpreg[25] /* caller saved 8 */
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#define k0Reg gpreg[26] /* kernal reserved 0 */
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#define k1Reg gpreg[27] /* kernal reserved 1 */
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#define gpReg gpreg[28] /* global pointer */
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#define spReg gpreg[29] /* stack pointer */
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#define s8Reg gpreg[30] /* callee saved 8 */
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#define fpReg s8Reg /* gcc says this is frame pointer */
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#define raReg gpreg[31] /* return address */
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#define reg_pc pc /* program counter */
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#define reg_sp spReg /* stack pointer */
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#define reg_fp fpReg /* frame pointer */
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#define SR_OFFSET (0*4) /* sr register offset */
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#define PC_OFFSET (1*4) /* pc register offset */
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#endif /* _ASMLANGUAGE */
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#define GREG_BASE (2*4+2*_RTypeSize)
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#define GREG_OFFSET(n) (GREG_BASE + (n)*_RTypeSize)
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#define SRREG (0*4) /* process status register */
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#define PCREG (1*4) /* program counter */
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#define LOREG (2*4+0*_RTypeSize) /* lo register */
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#define HIREG (2*4+1*_RTypeSize) /* hi register */
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#define ZEROREG GREG_OFFSET(0) /* wired zero */
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#define ATREG GREG_OFFSET(1) /* assembler temp */
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#define V0REG GREG_OFFSET(2) /* function return 0 */
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#define V1REG GREG_OFFSET(3) /* function return 1 */
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#define A0REG GREG_OFFSET(4) /* parameter 0 */
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#define A1REG GREG_OFFSET(5) /* parameter 1 */
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#define A2REG GREG_OFFSET(6) /* parameter 2 */
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#define A3REG GREG_OFFSET(7) /* parameter 3 */
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#define T0REG GREG_OFFSET(8) /* caller saved 0 */
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#define T1REG GREG_OFFSET(9) /* caller saved 1 */
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#define T2REG GREG_OFFSET(10) /* caller saved 2 */
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#define T3REG GREG_OFFSET(11) /* caller saved 3 */
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#define T4REG GREG_OFFSET(12) /* caller saved 4 */
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#define T5REG GREG_OFFSET(13) /* caller saved 5 */
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#define T6REG GREG_OFFSET(14) /* caller saved 6 */
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#define T7REG GREG_OFFSET(15) /* caller saved 7 */
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#define S0REG GREG_OFFSET(16) /* callee saved 0 */
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#define S1REG GREG_OFFSET(17) /* callee saved 1 */
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#define S2REG GREG_OFFSET(18) /* callee saved 2 */
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#define S3REG GREG_OFFSET(19) /* callee saved 3 */
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#define S4REG GREG_OFFSET(20) /* callee saved 4 */
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#define S5REG GREG_OFFSET(21) /* callee saved 5 */
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#define S6REG GREG_OFFSET(22) /* callee saved 6 */
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#define S7REG GREG_OFFSET(23) /* callee saved 7 */
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#define T8REG GREG_OFFSET(24) /* caller saved 8 */
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#define T9REG GREG_OFFSET(25) /* caller saved 8 */
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#define K0REG GREG_OFFSET(26) /* kernal reserved 0 */
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#define K1REG GREG_OFFSET(27) /* kernal reserved 1 */
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#define GPREG GREG_OFFSET(28) /* global pointer */
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#define SPREG GREG_OFFSET(29) /* stack pointer */
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#define S8REG GREG_OFFSET(30) /* callee saved 8 */
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#define RAREG GREG_OFFSET(31) /* return address */
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#define GREG_END (GREG_BASE+32*_RTypeSize)
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#define WDBCAUSEREG (GREG_END+0*4) /* Cause reg (for wdb) */
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#define WDBFPCSRREG (GREG_END+1*4) /* FPCSR reg (for wdb) */
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#define INTCTRLREG (GREG_END+2*4) /* ext intr control reg */
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#define ULEXTRA1 (GREG_END+3*4) /* extra - 4 bytes pad */
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#define TLBHIREG (GREG_END+4*4+0*_RTypeSize) /* adrs spc id reg */
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#define RTEXTRA2 (GREG_END+4*4+1*_RTypeSize) /* extra */
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#define RTEXTRA3 (GREG_END+4*4+2*_RTypeSize) /* extra */
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#define RTEXTRA4 (GREG_END+4*4+3*_RTypeSize) /* extra */
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#define RTEXTRA5 (GREG_END+4*4+4*_RTypeSize) /* extra */
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#define RTEXTRA6 (GREG_END+4*4+5*_RTypeSize) /* extra */
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#define RTEXTRA7 (GREG_END+4*4+6*_RTypeSize) /* extra */
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#define RTEXTRA8 (GREG_END+4*4+7*_RTypeSize) /* extra */
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#define RTEXTRA9 (GREG_END+4*4+8*_RTypeSize) /* extra */
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#define RTEXTRA10 (GREG_END+4*4+9*_RTypeSize) /* extra */
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#if defined(_WRS_CAVIUM_CNMIPS_CORE) || defined(_WRS_CAVIUM_CNMIPS_II_CORE)
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#define P0REG RTEXTRA3
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#define P1REG RTEXTRA4
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#define P2REG RTEXTRA5
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#define MPL0REG RTEXTRA6
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#define MPL1REG RTEXTRA7
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#define MPL2REG RTEXTRA8
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#define TLOREG RTEXTRA9
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#define THIREG RTEXTRA10
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#endif /* defined(_WRS_CAVIUM_CNMIPS_CORE) || defined(_WRS_CAVIUM_CNMIPS_II_CORE) */
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#if defined(_WRS_MIPS_NETLOGIC_CPU)
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/* Use RT Extra 3 for EIMRREG */
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#define EIMRREG RTEXTRA3
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#endif /* _WRS_MIPS_NETLOGIC_CPU */
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#define REG_SET_SIZE (GREG_END+4*4+10*_RTypeSize)
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCregsMipsh */
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