228 lines
7.9 KiB
C
228 lines
7.9 KiB
C
/* regsPpc.h - PowerPC registers */
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/* Copyright 1984-2008, 2010, 2011 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01n,03may11,syt add support for PPC465.
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01n,20aug10,x_z add support for PPC476.
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01m,03sep08,pmr remove SPE for e500mc
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01l,26oct06,to add WIND_CPU_STATE
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01k,15apr06,pch add REG_SET_SP
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01j,12feb04,jtp Apply _WRS_MMU_CLASS_* macros.
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01i,15jan04,jtp SPR 93230 - make PPC32 REG_SET struct size match other PPC.
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01h,01dec03,jtp Add PPC440 ASID storage; size & offset cleanup
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01g,13nov03,pcs Make the size of REG_SET the same for all CPU variants.
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01f,09oct03,pcs Add context information to the REG_SET.
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01f,03oct02,dtr Adding speFpscr to standard register set for 85XX.
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01e,30dec97,dbt added common names for registers
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01d,20apr95,yao add padding word for PPC604 and PPC603.
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01c,02mar95,yao changed PPC403GA to PPC403.
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01b,07nov94,yao moved tool related definition to tools.h.
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xxxxxxxxxxx,yao written.
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*/
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#ifndef __INCregsPpch
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#define __INCregsPpch
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define GREG_NUM 32 /* has 32 32/64-bit data registers */
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#ifndef _ASMLANGUAGE
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typedef struct /* REG_SET */
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{
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_RType gpr[GREG_NUM]; /* general purpose registers */
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_RType msr; /* machine state register */
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_RType lr; /* link register */
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_RType ctr; /* count register */
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_RType pc; /* program counter */
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UINT32 cr; /* condition register */
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UINT32 xer; /* fixed-point exception register */
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#if (CPU==PPC601)
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UINT32 mq; /* MQ register */
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#else
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UINT32 pgTblPtr; /* base of page table */
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#endif /* (CPU==PPC601) */
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#if defined(_WRS_MMU_CLASS_SR_REGS)
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UINT32 scSrTblPtr; /* SR regs array ptr - kernel protection map */
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UINT32 srTblPtr; /* SR regs array ptr - user protection map */
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#elif defined(_WRS_MMU_CLASS_PID_REG)
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UINT32 casid; /* PPC405, Book E PID and PPC860 M_CASID */
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# if (CPU == PPC85XX)
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UINT32 spefscr; /* SPE floating-point status & ctrl reg */
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# else /* CPU == PPC85XX */
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UINT32 spare1; /* keeps struct size consistent */
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# endif /* CPU == PPC85XX */
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#else /* _WRS_MMU_CLASS_ */
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UINT32 spare0; /* keeps struct size consistent */
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UINT32 spare1; /* keeps struct size consistent */
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#endif /* _WRS_MMU_CLASS_* */
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} REG_SET;
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typedef struct wind_cpu_state
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{
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REG_SET regs;
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} WIND_CPU_STATE;
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/* some common names for registers */
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#undef spReg
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#define spReg gpr[1] /* stack pointer */
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#undef fpReg
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#define fpReg gpr[31] /* frame pointer */
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#define reg_pc pc /* program counter */
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#define reg_sp spReg /* stack pointer */
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#define reg_fp fpReg /* frame pointer */
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#endif /* _ASMLANGUAGE */
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#define PPC_ARG0_REG 3 /* params start at register 3 */
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#define PPC_MAX_ARG_REGS 8 /* max # of params passed in register */
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#define REG_SET_GRBASE 0x00 /* general purpose register base */
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#define REG_SET_GR(n) (REG_SET_GRBASE + _PPC_REG_SIZE*(n))
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#define REG_SET_MSR (REG_SET_GR(GREG_NUM))
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#define REG_SET_LR (REG_SET_MSR + _PPC_REG_SIZE)
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#define REG_SET_CTR (REG_SET_LR + _PPC_REG_SIZE)
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#define REG_SET_PC (REG_SET_CTR + _PPC_REG_SIZE)
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#define REG_SET_CR (REG_SET_PC + _PPC_REG_SIZE)
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#define REG_SET_XER (REG_SET_CR + 4)
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#define REG_SET_SP (REG_SET_GR(1))
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#if (CPU==PPC601)
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#define REG_SET_MQ (REG_SET_XER + 4)
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#else /* (CPU==PPC601) */
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#define REG_SET_PG_TBL_PTR (REG_SET_XER + 4) /* ptr to pgTbl */
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#endif /* (CPU==PPC601) */
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#if defined(_WRS_MMU_CLASS_SR_REGS)
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#define REG_SET_SC_SR_TBL_PTR (REG_SET_PG_TBL_PTR + 4)
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#define REG_SET_SR_TBL_PTR (REG_SET_SC_SR_TBL_PTR + 4)
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#elif defined(_WRS_MMU_CLASS_PID_REG)
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#define REG_SET_CASID (REG_SET_PG_TBL_PTR + 4) /* current ASID */
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#if (CPU == PPC85XX)
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#ifdef _WRS_SPE_SUPPORT
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#define REG_SET_SPEFSCR (REG_SET_CASID + 4)
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#endif /* _WRS_SPE_SUPPORT */
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#endif /* CPU == PPC85XX */
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#endif /* _WRS_MMU_CLASS_* */
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#define PC_OFFSET REG_SET_PC
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#define WIND_TCB_R0 (WIND_TCB_REGS + REG_SET_GR(0))
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#define WIND_TCB_R1 (WIND_TCB_REGS + REG_SET_GR(1))
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#define WIND_TCB_R2 (WIND_TCB_REGS + REG_SET_GR(2))
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#define WIND_TCB_R3 (WIND_TCB_REGS + REG_SET_GR(3))
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#define WIND_TCB_R4 (WIND_TCB_REGS + REG_SET_GR(4))
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#define WIND_TCB_R5 (WIND_TCB_REGS + REG_SET_GR(5))
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#define WIND_TCB_R6 (WIND_TCB_REGS + REG_SET_GR(6))
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#define WIND_TCB_R7 (WIND_TCB_REGS + REG_SET_GR(7))
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#define WIND_TCB_R8 (WIND_TCB_REGS + REG_SET_GR(8))
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#define WIND_TCB_R9 (WIND_TCB_REGS + REG_SET_GR(9))
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#define WIND_TCB_R10 (WIND_TCB_REGS + REG_SET_GR(10))
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#define WIND_TCB_R11 (WIND_TCB_REGS + REG_SET_GR(11))
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#define WIND_TCB_R12 (WIND_TCB_REGS + REG_SET_GR(12))
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#define WIND_TCB_R13 (WIND_TCB_REGS + REG_SET_GR(13))
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#define WIND_TCB_R14 (WIND_TCB_REGS + REG_SET_GR(14))
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#define WIND_TCB_R15 (WIND_TCB_REGS + REG_SET_GR(15))
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#define WIND_TCB_R16 (WIND_TCB_REGS + REG_SET_GR(16))
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#define WIND_TCB_R17 (WIND_TCB_REGS + REG_SET_GR(17))
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#define WIND_TCB_R18 (WIND_TCB_REGS + REG_SET_GR(18))
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#define WIND_TCB_R19 (WIND_TCB_REGS + REG_SET_GR(19))
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#define WIND_TCB_R20 (WIND_TCB_REGS + REG_SET_GR(20))
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#define WIND_TCB_R21 (WIND_TCB_REGS + REG_SET_GR(21))
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#define WIND_TCB_R22 (WIND_TCB_REGS + REG_SET_GR(22))
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#define WIND_TCB_R23 (WIND_TCB_REGS + REG_SET_GR(23))
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#define WIND_TCB_R24 (WIND_TCB_REGS + REG_SET_GR(24))
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#define WIND_TCB_R25 (WIND_TCB_REGS + REG_SET_GR(25))
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#define WIND_TCB_R26 (WIND_TCB_REGS + REG_SET_GR(26))
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#define WIND_TCB_R27 (WIND_TCB_REGS + REG_SET_GR(27))
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#define WIND_TCB_R28 (WIND_TCB_REGS + REG_SET_GR(28))
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#define WIND_TCB_R29 (WIND_TCB_REGS + REG_SET_GR(29))
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#define WIND_TCB_R30 (WIND_TCB_REGS + REG_SET_GR(30))
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#define WIND_TCB_R31 (WIND_TCB_REGS + REG_SET_GR(31))
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#define WIND_TCB_MSR (WIND_TCB_REGS + REG_SET_MSR)
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#define WIND_TCB_LR (WIND_TCB_REGS + REG_SET_LR)
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#define WIND_TCB_CTR (WIND_TCB_REGS + REG_SET_CTR)
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#define WIND_TCB_PC (WIND_TCB_REGS + REG_SET_PC)
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#define WIND_TCB_CR (WIND_TCB_REGS + REG_SET_CR)
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#define WIND_TCB_XER (WIND_TCB_REGS + REG_SET_XER)
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#if (CPU==PPC601)
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#define WIND_TCB_MQ (WIND_TCB_REGS + REG_SET_MQ)
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#else /* (CPU==PPC601) */
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#define WIND_TCB_PG_TBL_PTR (WIND_TCB_REGS + REG_SET_PG_TBL_PTR)
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#endif /* (CPU==PPC601) */
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#if defined(_WRS_MMU_CLASS_SR_REGS)
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#define WIND_TCB_SC_SR_TBL_PTR (WIND_TCB_REGS + REG_SET_SC_SR_TBL_PTR)
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#define WIND_TCB_SR_TBL_PTR (WIND_TCB_REGS + REG_SET_SR_TBL_PTR)
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#elif defined(_WRS_MMU_CLASS_PID_REG)
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#define WIND_TCB_CASID (WIND_TCB_REGS + REG_SET_CASID)
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#if (CPU == PPC85XX)
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#ifdef _WRS_SPE_SUPPORT
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#define WIND_TCB_SPEFSCR (WIND_TCB_REGS + REG_SET_SPEFSCR)
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#endif /* _WRS_SPE_SUPPORT */
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#endif /* CPU == PPC85XX */
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#endif /* _WRS_MMU_CLASS_* */
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#define WIND_TCB_SP WIND_TCB_R1
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#define WIND_TCB_P0 WIND_TCB_R3
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#define WIND_TCB_P1 WIND_TCB_R4
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#define WIND_TCB_P2 WIND_TCB_R5
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#define WIND_TCB_P3 WIND_TCB_R6
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#define WIND_TCB_P4 WIND_TCB_R7
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#define WIND_TCB_P5 WIND_TCB_R8
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#define WIND_TCB_P6 WIND_TCB_R9
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#define WIND_TCB_P7 WIND_TCB_R10
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#define WIND_TCB_T0 WIND_TCB_R14
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#define WIND_TCB_T1 WIND_TCB_R15
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#define WIND_TCB_T2 WIND_TCB_R16
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#define WIND_TCB_T3 WIND_TCB_R17
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#define WIND_TCB_T4 WIND_TCB_R18
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#define WIND_TCB_T5 WIND_TCB_R19
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#define WIND_TCB_T6 WIND_TCB_R20
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#define WIND_TCB_T7 WIND_TCB_R21
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#define WIND_TCB_T8 WIND_TCB_R22
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#define WIND_TCB_T9 WIND_TCB_R23
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#define WIND_TCB_T10 WIND_TCB_R24
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#define WIND_TCB_T11 WIND_TCB_R25
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#define WIND_TCB_T12 WIND_TCB_R26
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#define WIND_TCB_T13 WIND_TCB_R27
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#define WIND_TCB_T14 WIND_TCB_R28
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#define WIND_TCB_T15 WIND_TCB_R29
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#define WIND_TCB_T16 WIND_TCB_R30
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#define WIND_TCB_T17 WIND_TCB_R31
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#ifdef _AIX_TOOL
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#define WIND_TCB_RTOC WIND_TCB_R2
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#endif /* _AIX_TOOL */
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/* size of the full REG_SET structure, including spare bytes */
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#define _PPC_REG_SET_SIZE (_PPC_REG_SIZE * (GREG_NUM + 9))
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#if (CPU == PPC860)
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/* Last valid number for the ASID register on the 8xx family */
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#define LAST_ASID 15
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#elif ((CPU == PPC405) || (CPU == PPC440) || (CPU == PPC85XX) || (CPU == PPC465))
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#define LAST_ASID 255
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#elif (CPU == PPC476)
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#define LAST_ASID 65535
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCregsPpch */
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