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m241Neelima/vxworks-6.9/target/h/drv/wlan/dot11Bsp.h
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2026-07-30 11:19:44 +05:30

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5.6 KiB
C

/* dot11Bsp.h - Contains definitions used to communicate with the BSP */
/* Copyright 2004 Wind River Systems, Inc. */
/*
Modification History
--------------------
02g,27feb08,hfc added entries for vxbus driver
02f,01mar07,spw Moved device / vendor id definitions to this file
02e,09sep05,rb Added countryCode as boot parameter
02d,25jan05,rb Made security components optionally buildable
02c,07jan05,rb Added members to dot11BspFuncs for 802.1X Integration
02b,01nov04,rb Added settings for security policy
02a,25aug04,rb Wind River Wireless Ethernet Driver 2.0 FCS
*/
/*
DESCRIPTION
This file contains the definitions necessary for the DOT11 Frameowrk to load
the Atheros cards from the BSP, as defined in sysAr521xEnd.c
*/
#ifndef __INCdot11Bsph
#define __INCdot11Bsph
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#ifdef VXBUS
#include <hwif/vxbus/vxBus.h>
#include <../src/hwif/h/vxbus/vxbAccess.h>
#include <hwif/vxbus/vxbPciLib.h>
#include <hwif/util/vxbDmaBufLib.h>
#include <hwif/util/vxbParamSys.h>
#endif /*VXBUS*/
/* This structure is used to hold basic default WLAN configuration parameters
that are used by the device driver on start up. They can be defined by
the user through the project facility or by making modifications to this
file and using the command line build option */
typedef struct dot11_default_config_s
{
char* ssid; /* Default SSID */
UINT32 mode; /* Default Station mode */
UINT32 radio; /* Default radio */
UINT32 channel; /* Default channel */
UINT32 country;
UINT32 secPol; /* Security Policy : a bitmap of allowed sec. policies */
UINT32 authPol; /* Authentication Policy: specifies 802.1X or PSK */
UINT32 ciphPol; /* Cipher Policy: Specifies list of allowed ciphers */
UINT8 preSharedKey[64]; /* If authPol == PSK, then this contains the PSK*/
char * rsnPassphrase;
} DOT11_DEFAULT_CONFIG;
#ifndef VXBUS
typedef struct dot11_bsp_func
{
/* Connect interrupt handler to vector */
void (*sysIntConnect)(int, int, int, STATUS*);
/* Disconnect interrupt handler from vector */
void (*sysIntDisconnect)(int, int, int, STATUS*);
/* System level interrupt enable */
void (*sysIntEnable)(INT32, STATUS*);
/* System level interrupt disable */
void (*sysIntDisable)(INT32, STATUS*);
/* Micro second delay */
void (*sysUsDelay)(int);
/* Cache invalidate function */
STATUS (*sysCacheInvalidate)(void*, UINT32);
/* Cache flush function */
STATUS (*sysCacheFlush)(void*, UINT32);
/* Converts bus address to CPU address */
UINT32 (*sysPhysToVirt) (UINT32);
/* Converts CPU address to bus address */
UINT32 (*sysVirtToPhys) (UINT32);
/* Write buffer flush function */
STATUS (*sysWbufFlush)();
/* Memory poll deallocation function */
void (*sysDmaMemFree)(UINT32);
/* SME types declared here so that the configlettes / cmd line can
include or exclude them at will */
STATUS (*essInit)(DOT11_FW*);
STATUS (*ibssInit)(DOT11_FW*);
STATUS (*apInit)(DOT11_FW*);
STATUS (*rsnInit)(DOT11_FW*);
} DOT11_BSP_FUNC;
typedef struct dot11_bsp_info
{
UINT32 magicNum; /* version */
UINT32 memBaseAddr; /* Mem base */
UINT32 ivec; /* IRQ vector */
UINT32 ilevel; /* IRQ level */
UINT16 pciVendorId; /* PCI Vendor Id */
UINT16 pciSubVendorId; /* PCI Subvendor Id*/
UINT16 pciDeviceId; /* PCI Dev ID */
UINT16 pciSubDeviceId; /* PCI Sub dev Id */
UINT32 dmaBuffAddr; /* DMA buffer addr */
UINT32 dmaBufSize; /* dma Buffer Size */
UINT32 cacheLineSz; /* cache line size */
UINT32 cfgFlag; /* configuration flag */
UINT8 pciChipSetRev; /* chipset version */
DOT11_BSP_FUNC* binding; /* access function provided by BSP */
DOT11_DEFAULT_CONFIG* config; /* Default configuration */
} DOT11_BSP_INFO;
#endif /* VXBUS */
#define DOT11_BSP_INFO_VER_0 0x1001
/*
* Supported device and vendor IDs of AR521X devices. Newer chipset
* versions or OEM versions will likely need new PCI_DEVICE_ID and/or
* PCI_VENDOR_ID entries.
*/
/* AR5211 */
#define AR5211_VENDOR_ID (0x168C)
#define AR5211_DEFAULT (0x1112) /* No eeprom HW default */
#define AR5311_DEVID (0x0011) /* Final ar5311 devid */
#define AR5211_DEVID (0x0012) /* Final ar5211 devid */
#define AR5211_LEGACY (0xFF12) /* Original emulation board */
#define AR5211_FPGA11B (0xF11B) /* 11b emulation board */
#define AR5211_SREV_1_0 (0x40)
#define AR5211_SREV_1_1 (0x42)
#define AR5211_SREV_REG (0x4020)
/* AR5212 */
#define AR5212_VENDOR_ID (0x168C)
#define AR5212_DEFAULT (0x1113) /* No eeprom HW default */
#define AR5212_DEVID (0x0013) /* ar5212 devid */
#define AR5312_DEVID (0x0030) /* Final ar5312 devid */
#define AR5212_SREV_1_0 (0x50)
#define AR5212_SREV_1_1 (0x51)
#define AR5212_SREV_1_3 (0x53)
#define AR5212_SREV_1_4 (0x56)
#define AR5212_SREV_REG (0x4020)
/* AR5212 compatible devid's also attach to 5212 */
#define AR5212_DEVID_0014 (0x0014) /* ar5212 forward compatibility id */
#define AR5212_DEVID_0015 (0x0015) /* ar5212 forward compatibility id */
#define AR5212_DEVID_0016 (0x0016) /* ar5212 forward compatibility id */
#define AR5212_DEVID_0017 (0x0017) /* ar5212 forward compatibility id */
#define AR5212_DEVID_0018 (0x0018) /* ar5212 forward compatibility id */
#define AR5212_DEVID_0019 (0x0019) /* ar5212 forward compatibility id */
#define AR5212_DEVID_001A (0x001A) /* ar5212 forward compatibility id */
#define AR5212_DEVID_001B (0x001B) /* ar5212 forward compatibility id */
/* AR5213 */
#define AR5213_SREV_1_0 (0x55)
#define AR5213_SREV_REG (0x4020)
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __INCdot11Bsph */