184 lines
6.1 KiB
C
184 lines
6.1 KiB
C
/* iPIIX4Dma.h - Intel 82371ab PCI-TO-ISA/IDEXCELERATOR(PIIX4) Driver Header file */
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/*
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* Copyright (c) 2001, 2005, 2007, 2010 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify, or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01g,06jul10,sye Add support to 82801DB(ICH4). (WIND00125477)
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01f,29apr10,pad Moved extern C statement after include statements.
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01e,15jun07,dee WIND00097125 - support 82801 and 6300esb I/O hub controllers
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01d,23sep05,dee SPR#112529, define additional dma controller pci types
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01c,02aug05,dee dma support for PIIX4 ATA controller
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01b,20dec01,bsp function declaration changed.
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01a,21Nov01,bsp written.
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*/
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/*
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* Please refer to Intel Document Order Number: 290562-001
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* 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
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*/
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#ifndef __INCiPIIX4Dmah
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#define __INCiPIIX4Dmah
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#ifndef _ASMLANGUAGE
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/* includes */
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#include <vxWorks.h>
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#include <drv/pci/pciConfigLib.h>
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#include <drv/pci/pciHeaderDefs.h>
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#include <wdLib.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* defines */
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#define I82371AB_VENDOR_ID 0x8086 /* Intel Corp. */
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#define I82371AB_DEVICE_ID 0x7111 /* i82371AB PIIX4 */
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#define I82801AA_DEVICE_ID 0x2411 /* i82801AA ICH */
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#define I82801AB_DEVICE_ID 0x2421 /* i82801AB ICH0 */
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#define I82801DB_DEVICE_ID 0x24CB /* i82801DB ICH4 */
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#define I82801_ICH6_DEVICE_ID 0x2651 /* i82801FB ICH6 sata */
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#define I82801FB_DEVICE_ID 0x266F /* i82801FB ICH6 ide */
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#define I82801_ICH7A_DEVICE_ID 0x27C4 /* i82801FB ICH7 sata */
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#define I82801_ICH7B_DEVICE_ID 0x27C0 /* i82801FB ICH7 ata */
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#define I82372FB_DEVICE_ID 0x7601 /* i82372FB */
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#define I6300ESB_P_DEVICE_ID 0x25A2 /* 6300esb ata mode */
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#define I6300ESB_C_DEVICE_ID 0x25A3 /* 6300esb combined mode */
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#define I82371AB_MAC_64_K 0x10000 /* pow(2,16) */
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#define I82371AB_MAC_4_K 0x01000 /* pow(2,12) */
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#define I82371AB_MAC_512 0x00200 /* pow(2,9) */
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/* max number of controllers */
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#define I82371AB_MAX_CTRLS 0x2 /* 0 and 1 only */
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/* Offset in the PCI configuaration space */
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#define PCI_CFG_BMIBA PCI_CFG_BASE_ADDRESS_4
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/* 0x20-0x23 default = 0x0000 R/W */
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#define PCI_CFG_IDETIM(ctrl) (0x40 + ctrl * 2)
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#define PCI_CFG_IDETIM_PRI 0x40 /* 0x40-0x41 default = 0x0000 R/W */
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#define PCI_CFG_IDETIM_SEC 0x42 /* 0x42-0x43 default = 0x0000 R/W */
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#define PCI_CFG_SIDETIME 0x44 /* 0x44 default = 0x00 R/W */
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#define PCI_CFG_UDMACTL 0x48 /* 0x48 default = 0x00 R/W */
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#define PCI_CFG_UDMATIM 0x4A /* 0x4A-0x4B default = 0x0000 R/W */
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/* Page-78, 2.7, Ref-1 */
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#define I82371AB_BMICOMadd(ctrl) (ideController.ioBaseAddress + 0x0 + ctrl * 8)
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#define I82371AB_BMISTAadd(ctrl) (ideController.ioBaseAddress + 0x2 + ctrl * 8)
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#define I82371AB_BMIDTPadd(ctrl) (ideController.ioBaseAddress + 0x4 + ctrl * 8)
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#define I82371AB_BMI_ALL 0xff
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#define I82371AB_BMICOM 0x00
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#define I82371AB_BMISTA 0x01
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#define I82371AB_BMIDTP 0x02
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/* BMICOM */
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#define I82371AB_RWCON 0x08
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#define I82371AB_SSBM 0x01
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/* BMISTA */
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#define I82371AB_DMA1CAP 0x40
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#define I82371AB_DMA0CAP 0x20
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#define I82371AB_INT_STATUS 0x04
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#define I82371AB_IDEDMA_ERROR 0x02
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#define I82371AB_BMIDE_ACTIVE 0x01
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/* bit masks */
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#define I82371AB_BMBIA_ADD_MASK 0xfff0 /* valid bits 15 to 4 */
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/* PCI status */
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#define I82371AB_PCISTS_BME 0x0004 /* bus master enable bit*/
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#define I82371AB_PCISTS_IOSE 0x0001 /* I/O space enable bit */
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/* IDE Timing Register */
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#define I82371AB_IDETIM_ENE 0x8000 /* IDE enable */
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#define I82371AB_IDETIM_PPE0 0x0004 /* PPC0 enable */
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#define I82371AB_IDETIM_IE0 0x0002 /* IORDY Sample Point
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Enable Drive 0 */
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/* A small delay for register hardware settling time*/
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#define I82371AB_DELAY(ctrl) sysInByte(I82371AB_BMISTAadd(ctrl)); \
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sysInByte(I82371AB_BMISTAadd(ctrl)); \
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sysInByte(I82371AB_BMISTAadd(ctrl)); \
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sysInByte(I82371AB_BMISTAadd(ctrl))
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/* typedefs */
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typedef struct pci_ide_controller
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{
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int pciBusNo;
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int pciDeviceNo;
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int pciFuncNo;
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/* PCI configuaration Registers */
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PCI_HEADER_DEVICE pciHeader;
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UINT16 ideTim[2]; /* Primary channel - 40,41 */
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/* Secondary channel - 42,43 */
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UINT8 slaveIdeTim; /* 44 */
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UINT8 uDmaCtl; /* 48 */
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UINT16 uDmaTime; /* 4A-4B */
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/* IO Space Registers */
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UINT32 ioBaseAddress;
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UINT8 bmiCom[2]; /* 0x00 */
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UINT8 bmiSta[2]; /* 0x02 */
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UINT32 bmiDtp[2]; /* 0x04 */
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WDOG_ID bmiWdogId[2];
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BOOL bmiWdogOkay[2];
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UINT32 * pPRDTable[I82371AB_MAX_CTRLS];
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}PCI_IDE_CONTROLLER;
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typedef struct i82371DescTable
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{
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void * buffer;
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UINT16 count;
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UINT16 eot;
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#define END_OF_TABLE 0x8000; /* end of table bit indication */
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} i82371_DESC_TBL;
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/* function declarations */
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extern STATUS iPIIX4PciIdeCtrlInit (int ctrl);
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extern STATUS iPIIX4InitAtaDmaEngine (int ctrl, int drive, char * pBuf,
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UINT32 bufLength, int direction);
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extern STATUS iPIIX4StartAtaDmaEngine (int ctrl);
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extern STATUS iPIIX4StopAtaDmaEngine (int ctrl);
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extern STATUS iPIIX4AtaDmaTrnsfrWait (int ctrl, int time);
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extern short iPIIX4AtaDmaModeNegotiate (short rwmode);
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extern void iPIIX4IdeCtrlReset (void);
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extern STATUS iPIIX4AtaDmaModeSet (int ctrl,int drive,short rwmode);
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#ifdef IDEDMA_DEBUG
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extern void iPIIX4IdeDebugVerbosityLevelSet (int level);
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extern int iPIIX4IdeDebugVerbosityLevelGet (void);
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#endif /* IDEDMA_DEBUG */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCiPIIX4Dmah */
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