296 lines
11 KiB
C
296 lines
11 KiB
C
/* esfPpc.h - PowerPC exception stack frames */
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/*
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* Copyright (c) 1994-1996, 2000-2004, 2008-2010, 2012 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01y,05jul12,cww Fix _PPC_ESF_ESR macro for PPC465 and PPC476 (WIND00360186)
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01x,06apr12,cww add esr field for PPC4xx
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01w,03dec12,pcs Decouple macro PPC_e500mc for e6500 core.
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01x,05jul12,cww Fix _PPC_ESF_ESR macro for PPC465 and PPC476 (WIND00360186)
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01w,06apr12,cww add esr field for PPC4xx
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01v,20aug10,syt add support for PPC465.
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01u,20aug10,x_z add support for PPC476.
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01t,29apr10,pad Moved extern C statement after include statements.
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01t,24nov09,pmr remove extra word in e500mc ESF
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01s,29oct08,pmr conditionalize SPEFSCR on _WRS_SPE_SUPPORT
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01r,11sep08,pmr Fix WIND00134134
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01q,03sep08,pmr e500mc hard floating point
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01p,13feb08,pch CQ116232: mention DBSR overloading in 4xx ESF comments
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01o,23aug04,pch SPR 78780: split vecOffset into two UINT16's to make space
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to handle CI frameless nesting case
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01n,09jun04,pch add support for PPC440 with hard FP
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01m,12feb04,jtp Apply _WRS_MMU_CLASS_* macros.
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01l,13aug03,mil Consolidated esr and mcsr as well as dear and mcar for e500.
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01k,11nov02,mil Added E500 registers to ESF.
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01j,03oct02,dtr Adding spefscr register offset to regset in ESF.
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01l,01dec03,jtp PPC440/405 context switching support; size & offset cleanup
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01k,09oct03,pcs Add the context related register offset on exception stack.
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01j,14jan03,pch Add support for 440x5 core (PPC440GX)
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01i,22aug01,pch Replace "sizeof(UINT32)" with SIZ_UINT32 because the
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assembler barfs on the former.
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01h,15aug01,pch Add PPC440, remove an old "#if 0" block
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01g,25oct00,s_m renamed PPC405 cpu types
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01f,31aug00,sm added cases for PPC405 and PPC405F
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01e,04mar96,tam added support for PPC403.
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01d,20apr95,yao add padding word that esf stack size are same
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for all cpu variations.
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01c,06oct94,yao changed to put sp on the top of the stack.
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01b,29sep94,yao fixed register offset on the exception stack in
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correct order.
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01a,07jul94,yao written.
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*/
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#ifndef __INCesfPpch
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#define __INCesfPpch
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#include "regs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* excALib.s treats resumeOffset and vecOffset together as a 32-bit fullword,
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* thereby setting resumeOffset to zero. The only time when resumeOffset
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* is non-zero is when intCrtEnt detects frameless nesting of a critical
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* interrupt within the first few instructions of a normal event vector; in
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* this case resumeOffset is used to record the offset of the interrupted
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* normal vector so that it can be resumed properly after the critical
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* interrupt has been serviced. See comments in intCrtEnt for further
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* details.
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*
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* All C code now accesses vecOffset as a 16-bit halfword. Only assembly
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* code uses resumeOffset.
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*/
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#ifndef _ASMLANGUAGE
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typedef struct
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{
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_RType spCopy; /* unused - redundant copy of regSet.gpr[1] */
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UINT16 resumeOffset; /* resume offset for CI frameless nesting */
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UINT16 vecOffset; /* vector offset */
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UINT32 _errno; /* error number */
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# if ((CPU == PPC403) || (CPU == PPC405) || (CPU == PPC405F))
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_RType dear; /* data exception address register */
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UINT32 bear; /* bus error address register */
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UINT32 besr; /* bus error syndrome register, or DBSR */
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# elif ((CPU == PPC440) || (CPU == PPC476) || (CPU == PPC465))
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_RType dear; /* data exception address register */
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# ifdef _PPC_MSR_FP
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UINT32 fpcsr; /* floating-point control and status register */
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# else /* _PPC_MSR_FP */
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UINT32 pad3;
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# endif /* _PPC_MSR_FP */
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UINT32 mcsr; /* machine check status reg, ESR, or DBSR */
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# elif (CPU == PPC85XX)
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_RType dear; /* data exception address register and MCAR */
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UINT32 esr; /* exception syndrome register and MCSR/DBSR */
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UINT32 iarr; /* instruction address resume register */
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# else /* CPU == PPC4xx/PPC85xx */
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_RType dar; /* data address register */
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UINT32 dsisr; /* data storage interrupt status register */
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UINT32 fpcsr; /* floating-point control and status register */
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# endif /* CPU == PPC4xx/PPC85xx */
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REG_SET regSet; /* register set */
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# if (CPU == PPC440 && defined(PPC_440x5))
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UINT32 besr; /* bus error syndrome register */
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UINT32 bear_h; /* bus error address register (high) */
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UINT32 bear_l; /* bus error address register (low) */
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# else /* PPC440 && PPC_440x5 */
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# if (CPU == PPC405F) || defined (PPC_e500mc) || defined (PPC_e6500)
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UINT32 fpcsr; /* floating-point control and status register */
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# else /* CPU == PPC405F */
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UINT32 pad0;
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# endif /* CPU == PPC405F */
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UINT32 pad1;
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UINT32 pad2;
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# endif /* PPC440 && PPC_440x5 */
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#if ((CPU == PPC403) || (CPU == PPC405) || (CPU == PPC405F) || \
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(CPU == PPC440) || (CPU == PPC476) || (CPU == PPC465))
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UINT32 esr; /* exception syndrome register */
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#else /* PPC4xx */
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UINT32 pad4;
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#endif /* PPC4xx */
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} ESFPPC;
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#endif /* _ASMLANGUAGE */
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/* _PPC_ESF_SIZE provides sizeof(ESFPPC) for assembly language code */
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#define _PPC_ESF_SIZE (10 * _PPC_REG_SIZE + _PPC_REG_SET_SIZE)
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/* _PPC_ESF_STK_SIZE provides a stack-aligned ESFPPC allocation size */
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#define _PPC_ESF_STK_SIZE ((_PPC_ESF_SIZE + _STACK_ALIGN_SIZE - 1) & \
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~(_STACK_ALIGN_SIZE - 1))
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/* register offset on exception stack */
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/* Assembler barfs on sizeof(), so do it this way instead */
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#define SIZ_UINT32 4 /* sizeof(UINT32) */
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#define SIZ_UINT16 2 /* sizeof(UINT16) */
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#define _PPC_ESF_SP_OFF (0)
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#define _PPC_ESF_VEC_OFF (_PPC_ESF_SP_OFF + _PPC_REG_SIZE) /* fullword */
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#define _PPC_ESF_RES_OFF_H (_PPC_ESF_VEC_OFF + 0) /* halfword */
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#define _PPC_ESF_VEC_OFF_H (_PPC_ESF_VEC_OFF + SIZ_UINT16) /* halfword */
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#define _PPC_ESF_ERRNO (_PPC_ESF_VEC_OFF + SIZ_UINT32)
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#if ((CPU == PPC403) || (CPU == PPC405) || (CPU == PPC405F))
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# define _PPC_ESF_DEAR (_PPC_ESF_ERRNO + SIZ_UINT32)
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# define _PPC_ESF_BEAR (_PPC_ESF_DEAR + _PPC_REG_SIZE)
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# define _PPC_ESF_BESR (_PPC_ESF_BEAR + SIZ_UINT32)
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# define _PPC_ESF_REG_BASE (_PPC_ESF_BESR + SIZ_UINT32)
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#elif ((CPU == PPC440) || (CPU == PPC476) || (CPU == PPC465))
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# define _PPC_ESF_DEAR (_PPC_ESF_ERRNO + SIZ_UINT32)
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# ifdef _PPC_MSR_FP
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# define _PPC_ESF_FPCSR (_PPC_ESF_DEAR + _PPC_REG_SIZE)
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# else /* _PPC_MSR_FP */
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# define _PPC_ESF_PAD3 (_PPC_ESF_DEAR + _PPC_REG_SIZE)
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# endif /* _PPC_MSR_FP */
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# define _PPC_ESF_MCSR (_PPC_ESF_DEAR + _PPC_REG_SIZE + SIZ_UINT32)
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# define _PPC_ESF_REG_BASE (_PPC_ESF_MCSR + SIZ_UINT32)
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#elif (CPU == PPC85XX)
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# define _PPC_ESF_DEAR (_PPC_ESF_ERRNO + SIZ_UINT32)
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# define _PPC_ESF_ESR (_PPC_ESF_DEAR + _PPC_REG_SIZE)
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# define _PPC_ESF_IARR (_PPC_ESF_ESR + SIZ_UINT32)
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# define _PPC_ESF_REG_BASE (_PPC_ESF_IARR + SIZ_UINT32)
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#else /* CPU == PPC4xx/PPC85xx */
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# define _PPC_ESF_DAR (_PPC_ESF_ERRNO + SIZ_UINT32)
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# define _PPC_ESF_DSISR (_PPC_ESF_DAR + _PPC_REG_SIZE)
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# define _PPC_ESF_FPCSR (_PPC_ESF_DSISR + SIZ_UINT32)
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# define _PPC_ESF_REG_BASE (_PPC_ESF_FPCSR + SIZ_UINT32)
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#endif /* CPU == PPC4xx/PPC85xx */
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#if (CPU == PPC440 && defined(PPC_440x5))
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# define _PPC_ESF_BESR (_PPC_ESF_REG_BASE + _PPC_REG_SET_SIZE)
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# define _PPC_ESF_BEAR_H (_PPC_ESF_BESR + SIZ_UINT32)
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# define _PPC_ESF_BEAR_L (_PPC_ESF_BEAR_H + SIZ_UINT32)
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#else /* PPC440 && PPC_440x5 */
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# if (CPU == PPC405F) || defined (PPC_e500mc) || defined (PPC_e6500)
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# define _PPC_ESF_FPCSR (_PPC_ESF_REG_BASE + _PPC_REG_SET_SIZE)
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# define _PPC_ESF_PAD1 (_PPC_ESF_FPCSR + SIZ_UINT32)
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# else /* CPU == PPC405F */
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# define _PPC_ESF_PAD0 (_PPC_ESF_REG_BASE + _PPC_REG_SET_SIZE)
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# define _PPC_ESF_PAD1 (_PPC_ESF_PAD0 + SIZ_UINT32)
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# endif /* CPU == PPC405F */
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# define _PPC_ESF_PAD2 (_PPC_ESF_PAD1 + SIZ_UINT32)
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#endif /* PPC440 && PPC_440x5*/
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#if ((CPU == PPC403) || (CPU == PPC405) || (CPU == PPC405F) || \
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(CPU == PPC440) || (CPU == PPC476) || (CPU == PPC465))
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# ifdef PPC_440x5
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# define _PPC_ESF_ESR (_PPC_ESF_BEAR_L + SIZ_UINT32)
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# else
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# define _PPC_ESF_ESR (_PPC_ESF_PAD2 + SIZ_UINT32)
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# endif
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#else
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# define _PPC_ESF_PAD4 (_PPC_ESF_PAD2 + SIZ_UINT32)
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#endif
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#define _PPC_ESF_R(n) (_PPC_ESF_REG_BASE + (n) * _PPC_REG_SIZE)
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#define _PPC_ESF_MSR _PPC_ESF_R(GREG_NUM)
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#define _PPC_ESF_LR _PPC_ESF_R(GREG_NUM + 1)
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#define _PPC_ESF_CTR _PPC_ESF_R(GREG_NUM + 2)
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#define _PPC_ESF_PC _PPC_ESF_R(GREG_NUM + 3)
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#define _PPC_ESF_CR _PPC_ESF_R(GREG_NUM + 4)
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#define _PPC_ESF_XER (_PPC_ESF_CR + 4)
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#if (CPU == PPC601)
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#define _PPC_ESF_MQ (_PPC_ESF_XER + 4)
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#else /* (CPU == PPC601) */
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#define _PPC_ESF_PG_TBL_PTR (_PPC_ESF_XER + 4)
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#endif /* (CPU == PPC601) */
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#if defined(_WRS_MMU_CLASS_SR_REGS)
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#define _PPC_ESF_SC_SR_TBL_PTR (_PPC_ESF_PG_TBL_PTR + 4)
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#define _PPC_ESF_SR_TBL_PTR (_PPC_ESF_SC_SR_TBL_PTR + 4)
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#elif defined(_WRS_MMU_CLASS_PID_REG)
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#define _PPC_ESF_ASID (_PPC_ESF_PG_TBL_PTR + 4)
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#if defined(_WRS_SPE_SUPPORT)
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#define _PPC_ESF_SPEFSCR (_PPC_ESF_ASID + 4)
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#endif /* _WRS_SPE_SUPPORT */
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#endif /* _WRS_MMU_CLASS_* */
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#define _PPC_ESF_R0 _PPC_ESF_R(0)
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#define _PPC_ESF_R1 _PPC_ESF_R(1)
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#define _PPC_ESF_R2 _PPC_ESF_R(2)
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#define _PPC_ESF_R3 _PPC_ESF_R(3)
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#define _PPC_ESF_R4 _PPC_ESF_R(4)
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#define _PPC_ESF_R5 _PPC_ESF_R(5)
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#define _PPC_ESF_R6 _PPC_ESF_R(6)
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#define _PPC_ESF_R7 _PPC_ESF_R(7)
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#define _PPC_ESF_R8 _PPC_ESF_R(8)
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#define _PPC_ESF_R9 _PPC_ESF_R(9)
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#define _PPC_ESF_R10 _PPC_ESF_R(10)
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#define _PPC_ESF_R11 _PPC_ESF_R(11)
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#define _PPC_ESF_R12 _PPC_ESF_R(12)
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#define _PPC_ESF_R13 _PPC_ESF_R(13)
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#define _PPC_ESF_R14 _PPC_ESF_R(14)
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#define _PPC_ESF_R15 _PPC_ESF_R(15)
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#define _PPC_ESF_R16 _PPC_ESF_R(16)
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#define _PPC_ESF_R17 _PPC_ESF_R(17)
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#define _PPC_ESF_R18 _PPC_ESF_R(18)
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#define _PPC_ESF_R19 _PPC_ESF_R(19)
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#define _PPC_ESF_R20 _PPC_ESF_R(20)
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#define _PPC_ESF_R21 _PPC_ESF_R(21)
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#define _PPC_ESF_R22 _PPC_ESF_R(22)
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#define _PPC_ESF_R23 _PPC_ESF_R(23)
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#define _PPC_ESF_R24 _PPC_ESF_R(24)
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#define _PPC_ESF_R25 _PPC_ESF_R(25)
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#define _PPC_ESF_R26 _PPC_ESF_R(26)
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#define _PPC_ESF_R27 _PPC_ESF_R(27)
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#define _PPC_ESF_R28 _PPC_ESF_R(28)
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#define _PPC_ESF_R29 _PPC_ESF_R(29)
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#define _PPC_ESF_R30 _PPC_ESF_R(30)
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#define _PPC_ESF_R31 _PPC_ESF_R(31)
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#define _PPC_ESF_P0 _PPC_ESF_R3
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#define _PPC_ESF_P1 _PPC_ESF_R4
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#define _PPC_ESF_P2 _PPC_ESF_R5
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#define _PPC_ESF_P3 _PPC_ESF_R6
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#define _PPC_ESF_P4 _PPC_ESF_R7
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#define _PPC_ESF_P5 _PPC_ESF_R8
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#define _PPC_ESF_P6 _PPC_ESF_R9
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#define _PPC_ESF_P7 _PPC_ESF_R10
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#define _PPC_ESF_T0 _PPC_ESF_R14
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#define _PPC_ESF_T1 _PPC_ESF_R15
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#define _PPC_ESF_T2 _PPC_ESF_R16
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#define _PPC_ESF_T3 _PPC_ESF_R17
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#define _PPC_ESF_T4 _PPC_ESF_R18
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#define _PPC_ESF_T5 _PPC_ESF_R19
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#define _PPC_ESF_T6 _PPC_ESF_R20
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#define _PPC_ESF_T7 _PPC_ESF_R21
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#define _PPC_ESF_T8 _PPC_ESF_R22
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#define _PPC_ESF_T9 _PPC_ESF_R23
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#define _PPC_ESF_T10 _PPC_ESF_R24
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#define _PPC_ESF_T11 _PPC_ESF_R25
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#define _PPC_ESF_T12 _PPC_ESF_R26
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#define _PPC_ESF_T13 _PPC_ESF_R27
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#define _PPC_ESF_T14 _PPC_ESF_R28
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#define _PPC_ESF_T15 _PPC_ESF_R29
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#define _PPC_ESF_T16 _PPC_ESF_R30
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#define _PPC_ESF_T17 _PPC_ESF_R31
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#define _PPC_ESF_SP _PPC_ESF_R1
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#ifdef _AIX_TOOL
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#define _PPC_ESF_RTOC _PPC_ESF_R(2)
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#endif /* _AIX_TOOL */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCesfPpch */
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