497 lines
17 KiB
C
497 lines
17 KiB
C
/* archPpc.h - PowerPC specific header */
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/*
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* Copyright (c) 1984-2012, 2014 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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10oct14,d_l remove PPC32 condition build for MSR and FPSCR bit definition.
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(VXW6-83572)
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03n,24jul12,h_k increased VX_MAX_SMP_CPUS to 32 for T4240 and future coming
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CPUs. (WIND00364728)
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03m,03may11,syt added support for PPC465
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03l,15dec10,pch CQ239447: add _WRS_ARCH_DEFERS_KERNEL_UNLOCK
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03k,14dec10,gls made VX_OBJ_ALIGN_SIZE constant across all variants
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(WIND00246452)
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03j,16sep10,gls added VX_OBJ_ALIGN_SIZE.
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03j,20aug10,x_z added support for PPC476.
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03i,29jul10,pad Moved extern C statement after include statements.
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03h,01oct09,pgh Remove _WRS_CHECK_MACHINE_TYPE macro.
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03g,28sep09,pgh Fix _WRS_CHECK_MACHINE_TYPE
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03g,08jul09,b_m added _PPC_WORD_SIZE.
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03f,31jul08,tcr change macro for compatibility
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03e,19may08,tcr update SV interrupt macro
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03d,25mar08,pch Limit VX_MAX_SMP_CPUS to 1 if LOG_FRAMELESS || LOG_DISPATCH
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03c,13mar08,rlp Removed obsolete _WRS_ARCH_HAS_DBG_IPI macro.
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03b,25feb08,pch Move SMP-dependent settings to private/smpPpcP.h
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03a,13sep07,pch CQ102745: add _ARCH_SUPPORTS_PROTECT_IDLE_TASK_STACK
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02z,16aug07,pch rename spinlockApiAvailable to spinLockApiAvailable
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02y,15aug07,mmi add _WRS_ARCH_HAS_CPU_PWR_MGMT and POW_MASK()
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02x,07aug07,pch CQ100667: define _WRS_ARCH_HAS_SPINLOCK_API_AVAILABLE
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in SMP build
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02w,01jun07,jmp Defined _WRS_ARCH_HAS_VXDBG_CPU_CTRL_SUPPORT for PPC.
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02v,04may07,zl updated portable library build configuration.
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02u,25apr07,kk move VX_MAX_SMP_CPUS to here
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02t,13apr07,rlp Added _WRS_ARCH_HAS_DBG_IPI macro.
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02s,21feb07,jmg Added include vxPortableP.h
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02r,11dec06,kk removed references to _WRS_BASE6_SCHEDULER, no longer needed
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02q,17oct06,lei removed _WRS_ARCH_HAS_RESCHEDULE_STACK;
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added _WRS_ARCH_HAS_IDLE_TASK
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02p,11oct06,mmi added _WRS_VX_NO_GLOBAL_ERRNO
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020,12sep06,lei added _WRS_ARCH_HAS_NEW_KERNEL_LOCK
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02m,04aug06,pch move SMP support to private/smpPpcP.h
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move kernel-only definitions here from asmPpc.h
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02l,28jul06,lei added _WRS_ARCH_HAS_RESCHEDULE_STACK
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02k,19jun06,pch SMP support
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02j,11apr05,kk removed _WRS_OBJLIB_SUPPORT_VERIFY_TRAP macro (SPR# 106486)
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02i,10feb05,pch SPR 102772: add _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
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02h,22apr04,to define RFI only for _ASMLANGUAGE
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02g,18mar04,rec merge in PPC970 changes
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02f,01nov04,pch SPR 92598: Add _WRS_OSM_INIT
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02e,01oct04,tam moved definition of _TYPE_PHYS_ADDR from shared file to
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kernel header
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02d,23aug04,aeg added _WRS_OBJLIB_SUPPORT_VERIFY_TRAP
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02c,11aug04,pch cleanup
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02b,11may04,tam removed _WRS_KERNEL_TEXT_START_ADRS definition
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02a,22mar04,zl moved trcLib_PORTABLE and INSTR definitions to archPpcCommon.h;
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added _WRS_FRAMEP_FROM_JMP_BUF and _WRS_RET_PC_FROM_JMP_BUF.
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01z,18feb04,zl defined trcLib_PORTABLE
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01y,03feb04,aeg moved _WRS_PAL_COPROC_LIB to archPpcCommon.h
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01x,27jan04,gls moved _TYPE_PHYS_ADDR definition to archPpcCommon.h
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01w,18dec03,dat temp fix for va_addr macro
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01v,14nov03,job Moved some blib stuff to archPpcCommon.h
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Added missing include of archPpcCommon.h
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01u,13nov03,pes Added include of archPpcCommon.h
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01t,14oct03,sru define 64-bit PHYS_ADDR type
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01s,10sep03,cjj removed dual definition of _WRS_ENABLE_IDLE_INTS
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01r,23apr03,pch Add generic PPC32 support
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01r,07may03,pes More conditional compilation cleanups.
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01q,02may03,pes PAL conditional compilation cleanup.
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01p,11apr03,pes Add define to trigger PAL Coprocessor Abstraction
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01o,09jul03,tam added macro _WRS_KERNEL_TEXT_START_ADRS
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01q,03dec02,mil Removed inclusion of ppc603.h for PPC85XX.
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01p,04sep02,dtr Adding 85XX header file.
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01o,02aug02,pcs Add support for PPC85XX and make it the same as PPC603 for
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the present.
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01n,13mar02,sn SPR 73723 - define supported toolchains
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01m,25sep01,yvp SPR62760 fix: Added default text segment alignment.
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01l,14aug01,pch Add PPC440 support
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01k,25oct00,s_m renamed PPC405 cpu types
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01j,12jun00,alp Added PPC405 support
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01i,12mar99,zl added PPC509 and PPC555 support.
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01h,18aug98,tpr added PowerPC EC 603 support.
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01g,10feb97,tam added FPSCR bit definition macros.
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01f,08oct96,tam added MSR bit definition macros.
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01e,11apr96,tpr added PPC505, PPC602 and PPC860.
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01d,14feb96,tpr added PPC604.
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01c,21mar95,caf moved _STACK_ALIGN_SIZE to toolPpc.h.
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01b,07nov94,yao changed PPC403GA to PPC403.
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01a,17mar94,yao written.
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*/
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#ifndef __INCarchPpch
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#define __INCarchPpch
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* temporary define */
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#define _WRS_VX_NO_GLOBAL_ERRNO
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/* arch supports deferred kernel unlock when configured for SMP and RTPs */
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#if defined(_WRS_CONFIG_SMP) && defined(_WRS_CONFIG_VM_MULTIPLE_CONTEXT)
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#define _WRS_ARCH_DEFERS_KERNEL_UNLOCK
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#endif /* _WRS_CONFIG_SMP && _WRS_CONFIG_VM_MULTIPLE_CONTEXT */
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/* define for SMP */
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#undef VX_MAX_SMP_CPUS
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#if defined(LOG_FRAMELESS) || defined(LOG_DISPATCH)
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#define VX_MAX_SMP_CPUS 1 /* maximum processors in SMP configuration */
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#else /* LOG_FRAMELESS || LOG_DISPATCH */
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#define VX_MAX_SMP_CPUS 32 /* maximum processors in SMP configuration */
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#endif /* LOG_FRAMELESS || LOG_DISPATCH */
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#define _ARCH_SUPPORTS_GCC
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#define _ARCH_SUPPORTS_DCC
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#if (CPU != PPC403)
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/* Used in usrDepend.c and usrKernelStack.c */
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#define _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
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#endif /* PPC403 */
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/* upper Machine State Register (MSR) mask */
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#define _PPC_MSR_SF_U 0x8000 /* sixty-four bit mode (not
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* implemented for 32-bit machine) */
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#define _PPC_MSR_POW_U 0x0004 /* power managemnet enable */
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#define _PPC_MSR_ILE_U 0x0001 /* little endian mode */
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/* lower Machine State Register (MSR) mask */
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#define _PPC_MSR_EE 0x8000 /* external interrupt enable */
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#define _PPC_MSR_PR 0x4000 /* privilege level */
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#define _PPC_MSR_FP 0x2000 /* floating-point available */
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#define _PPC_MSR_ME 0x1000 /* machine check enable */
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#define _PPC_MSR_FE0 0x0800 /* floating-point exception mode 0 */
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#define _PPC_MSR_SE 0x0400 /* single-step trace enable */
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#define _PPC_MSR_BE 0x0200 /* branch trace enable */
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#define _PPC_MSR_FE1 0x0100 /* floating-point exception mode 1 */
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#define _PPC_MSR_IP 0x0040 /* exception prefix */
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#define _PPC_MSR_IR 0x0020 /* instruction address translation */
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#define _PPC_MSR_DR 0x0010 /* data address translation */
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#define _PPC_MSR_RI 0x0002 /* recoverable interrupt */
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#define _PPC_MSR_LE 0x0001 /* little-endian mode */
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#define _PPC_MSR_POWERUP 0x0040 /* state of MSR at powerup */
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/* MSR bit definitions common to all PPC arch. */
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#define _PPC_MSR_BIT_EE 16 /* MSR Ext. Intr. Enable bit - EE */
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#define _PPC_MSR_BIT_PR 17 /* MSR Privilege Level bit - PR */
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#define _PPC_MSR_BIT_ME 19 /* MSR Machine Check Enable bit - ME */
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#define _PPC_MSR_BIT_LE 31 /* MSR Little Endian mode bit - LE */
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/* FPSCR bit definitions (valid for the PPC60X familly) */
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#define _PPC_FPSCR_FX 0x80000000 /* FP exception summary */
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#define _PPC_FPSCR_FEX 0x40000000 /* FP enabled exception summary */
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#define _PPC_FPSCR_VX 0x20000000 /* FP invalid exception summary */
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#define _PPC_FPSCR_OX 0x10000000 /* FP overflow exception */
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#define _PPC_FPSCR_UX 0x08000000 /* FP underflow exception */
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#define _PPC_FPSCR_ZX 0x04000000 /* FP divide by zero exception */
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#define _PPC_FPSCR_XX 0x02000000 /* FP inexact exception */
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#define _PPC_FPSCR_VXSNAN 0x01000000 /* FP invalid exception for SNAN */
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#define _PPC_FPSCR_VXISI 0x00800000 /* FP invalid exc. for INF-INF */
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#define _PPC_FPSCR_VXIDI 0x00400000 /* FP invalid exc. for INF/INF */
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#define _PPC_FPSCR_VXZDZ 0x00200000 /* FP invalid exc. for 0/0 */
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#define _PPC_FPSCR_VXIMZ 0x00100000 /* FP invalid exc. for INF*0 */
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#define _PPC_FPSCR_VXVC 0x00080000 /* FP inval. exc. for invalid comp.*/
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#define _PPC_FPSCR_FR 0x00040000 /* FP fraction rounded */
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#define _PPC_FPSCR_FI 0x00020000 /* FP fraction inexact */
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#define _PPC_FPSCR_FPRF 0x0001F000 /* FP result flags */
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#define _PPC_FPSCR_VXSOFT 0x00000400 /* FP inval. exc. for soft. request*/
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#define _PPC_FPSCR_VXSQRT 0x00000200 /* FP inval. exc. for sqrt */
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#define _PPC_FPSCR_VXCVI 0x00000100 /* FP inval. exc. for int convert */
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#define _PPC_FPSCR_VE 0x00000080 /* FP invalid exc. enable */
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#define _PPC_FPSCR_OE 0x00000040 /* FP overflow exc. enable */
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#define _PPC_FPSCR_UE 0x00000020 /* FP underflow exc. enable */
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#define _PPC_FPSCR_ZE 0x00000010 /* FP divide by zero exc. enable */
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#define _PPC_FPSCR_XE 0x00000008 /* FP iinexact exc. enable */
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#define _PPC_FPSCR_NI 0x00000004 /* FP non-IEEE mode enable */
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#define _PPC_FPSCR_RN(n) (n) /* FP rounding control value */
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#define _PPC_FPSCR_RN_MSK 0x00000003 /* FP rounding control bits mask */
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#define _PPC_FPSCR_EXC_MASK 0x1ff80700 /* FP exception status bits mask */
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#define _PPC_FPSCR_CTRL_MASK 0x000000ff /* FP exception control bits mask */
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/* FPSCR init value for tasks spawned with VX_FP_TASK (PPC60X only) */
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#define _PPC_FPSCR_INIT (_PPC_FPSCR_OE | _PPC_FPSCR_UE | _PPC_FPSCR_ZE \
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| _PPC_FPSCR_RN(0))
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#ifdef _ASMLANGUAGE
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#define RFI rfi
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#if (CPU != PPC32)
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#define DSISR 18 /* data storage interrupt status */
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#define DAR 19 /* data address register */
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#define DEC 22 /* decrement register */
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#define SDR1 25 /* storage description register 1 */
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#endif /* CPU != PPC32 */
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#define SRR0 26 /* save and restore register 0 */
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#define SRR1 27 /* save and restore register 1 */
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#define SPRG0 272 /* software program register 0 */
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#define SPRG1 273 /* software program register 1 */
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#define SPRG2 274 /* software program register 2 */
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#define SPRG3 275 /* software program register 3 */
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#if (CPU != PPC32)
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#define ASR 280 /* address space register
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* (64 bit implementation only) */
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#define EAR 282 /* external address register */
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#define TBL 284 /* lower time base register */
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#define TBU 285 /* upper time base register */
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#endif /* CPU != PPC32 */
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#define PVR 287 /* processor version register */
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#if (CPU != PPC32)
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#define IBAT0U 528 /* instruction BAT register */
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#define IBAT0L 529 /* instruction BAT register */
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#define IBAT1U 530 /* instruction BAT register */
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#define IBAT1L 531 /* instruction BAT register */
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#define IBAT2U 532 /* instruction BAT register */
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#define IBAT2L 533 /* instruction BAT register */
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#define IBAT3U 534 /* instruction BAT register */
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#define IBAT3L 535 /* instruction BAT register */
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#define DBAT0U 536 /* data BAT register */
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#define DBAT0L 537 /* data BAT register */
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#define DBAT1U 538 /* data BAT register */
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#define DBAT1L 539 /* data BAT register */
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#define DBAT2U 540 /* data BAT register */
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#define DBAT2L 541 /* data BAT register */
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#define DBAT3U 542 /* data BAT register */
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#define DBAT3L 543 /* data BAT register */
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#define IBAT4U 560 /* instruction BAT register */
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#define IBAT4L 561 /* instruction BAT register */
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#define IBAT5U 562 /* instruction BAT register */
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#define IBAT5L 563 /* instruction BAT register */
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#define IBAT6U 564 /* instruction BAT register */
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#define IBAT6L 565 /* instruction BAT register */
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#define IBAT7U 566 /* instruction BAT register */
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#define IBAT7L 567 /* instruction BAT register */
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#define DBAT4U 568 /* data BAT register */
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#define DBAT4L 569 /* data BAT register */
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#define DBAT5U 570 /* data BAT register */
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#define DBAT5L 571 /* data BAT register */
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#define DBAT6U 572 /* data BAT register */
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#define DBAT6L 573 /* data BAT register */
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#define DBAT7U 574 /* data BAT register */
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#define DBAT7L 575 /* data BAT register */
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/* macros to mask off particular bits of an MSR value */
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#ifndef INT_MASK
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#define INT_MASK(src, des) \
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rlwinm des, src, 0, _PPC_MSR_BIT_EE+1, _PPC_MSR_BIT_EE-1
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#endif /* INT_MASK */
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#define POW_MASK(src, des) \
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rlwinm des, src, 0, _PPC_MSR_BIT_POW+1, _PPC_MSR_BIT_POW-1
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#ifndef MMU_MASK
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/* Using bit #s here because names vary [DS,IS] vs [DR,IR] */
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#define MMU_MASK(src, des) rlwinm des, src, 0, 28, 25
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#endif /* MMU_MASK */
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#define RI_MASK(src, des) \
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rlwinm des, src, 0, _PPC_MSR_BIT_RI+1, _PPC_MSR_BIT_RI-1
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#define SE_MASK(src, des) \
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rlwinm des, src, 0, _PPC_MSR_BIT_SE+1, _PPC_MSR_BIT_SE-1
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#endif /* CPU != PPC32 */
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#else /* _ASMLANGUAGE */
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typedef unsigned int _RType; /* default register type */
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/* macros for getting frame and return PC from a jmp_buf */
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#define _WRS_FRAMEP_FROM_JMP_BUF(env) ((char *) (env)[0].reg.spReg)
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#define _WRS_RET_PC_FROM_JMP_BUF(env) ((INSTR *) (env)[0].reg.lr)
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/* physical addresses are represented on 64-bit for all PowerPC CPUs */
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#define _TYPE_PHYS_ADDR typedef UINT64 PHYS_ADDR
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#endif /* _ASMLANGUAGE */
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#define _WRS_PHYS_ADDR_IS_64_BITS
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#define _ARCH_MULTIPLE_CACHELIB FALSE
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#define _DYNAMIC_BUS_SIZING FALSE /* require alignment for swap */
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#define _PPC_REG_SIZE 4 /* default register size */
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#define _PPC_WORD_SIZE 32 /* number of bits in a word */
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#define _PPC_TEXT_SEG_ALIGN 4 /* 4 byte text segment alignment */
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#define RFI_OPCODE 0x4c000064
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/* PAL additions */
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/* moved here from h/private/eventP.h */
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/*
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* Macro for event logging of intEnt events for PPC architechtures.
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* The PPC architecture is different in that there is only one external
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* interrupt line coming into the CPU. At the time of the intEnt, the
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* external interrupt number is unknown, meaning that logging cannot
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* take place at this time. In this architechture, the logging of an
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* intEnt event is deferred until the interrupt controller driver
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* is exectued.
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* Since the logging has to take place in drivers and/or BSP world files,
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* the details of how the logging to be done has been deferred to a macro
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* which is defined here.
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*
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* Note: This replaces the previous technique of saving the timestamp
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* during the intEnt code to be used later, when the logging was done.
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* SPR 21868 refers to a problem in which this can give rise to out-of-order
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* timestamps in the event log.
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*/
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#define WV_EVT_INT_ENT(intNum) EVT_CTX_1(EVENT_INT_ENTER, intNum);
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/* moved here from h/private/javaLibP.h */
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#define JAVA_C_SYM_PREFIX ""
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/* moved here from h/private/loadElfLibP.h */
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#define LOW24_INSERT(buf,value) INSERT ((buf), (value), 0x03fffffc)
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/* define to pick up sysI/O function declarations in sysLib.h */
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#define _WRS_SYS_IO
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/* define to insert the evtLogT1_noTS() function into evtLogLib.c */
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#define _WRS_EVTLOGT1_NOTS
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/* temp fix for va_addr support (See SPR 92721) */
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#define _WRS_VA_ADDR(x) ((va_list *)x)
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/* from loadElfLib.c */
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#define _WRS_USE_ELF_LOAD_FORMAT
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/* from xdr_float.c */
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#define FLOAT_NORM
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/* from schedLib.c */
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#define _WRS_TASK_MSR_DEFAULT
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#define _WRS_VXLIB_SUPPORT
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/* used by reschedule() when the kernel is idle */
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#define _WRS_ENABLE_IDLE_INTS {intUnlock (taskMsrDefault);}
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/* PPC arch always requires OSM init if stack guard pages are enabled */
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#define _WRS_OSM_INIT
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/* temporary macro to indicate PPC uses the type II kernel lock */
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#define _WRS_ARCH_HAS_NEW_KERNEL_LOCK
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/* temporary macro to indicate PPC has idle task */
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#define _WRS_ARCH_HAS_IDLE_TASK
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/* indicates that PPC has VxDBG CPU control support */
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#define _WRS_ARCH_HAS_VXDBG_CPU_CTRL_SUPPORT
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/* indicates that PPC support cpu Power managment framework */
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#define _WRS_ARCH_HAS_CPU_PWR_MGMT
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/* End PAL */
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#ifdef __cplusplus
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}
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#endif
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|
|
|
|
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#if (CPU == PPC32)
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#include <arch/ppc/ppc32.h>
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#endif /* CPU == PPC32) */
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|
|
|
#if (CPU == PPC403)
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#include <arch/ppc/ppc403.h>
|
|
#endif /* CPU == PPC403) */
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|
|
|
#if ((CPU == PPC405) || (CPU == PPC405F))
|
|
#include <arch/ppc/ppc405.h>
|
|
#endif /* CPU == PPC405) || (CPU == PPC405F) */
|
|
|
|
#if ((CPU == PPC440) || (CPU == PPC465))
|
|
#include <arch/ppc/ppc440.h>
|
|
#endif /* (CPU == PPC440) || (CPU == PPC465) */
|
|
|
|
#if (CPU == PPC476)
|
|
#include <arch/ppc/ppc476.h>
|
|
#endif /* CPU == PPC476 */
|
|
|
|
#if (CPU == PPC509)
|
|
#include <arch/ppc/ppc509.h>
|
|
#endif /* CPU == PPC509) */
|
|
|
|
#if (CPU == PPC555)
|
|
#include <arch/ppc/ppc555.h>
|
|
#endif /* CPU == PPC555) */
|
|
|
|
#if (CPU == PPC601)
|
|
#include <arch/ppc/ppc601.h>
|
|
#endif /* CPU == PPC601) */
|
|
|
|
#if (CPU == PPC602)
|
|
#include <arch/ppc/ppc602.h>
|
|
#endif /* CPU == PPC602) */
|
|
|
|
#if ((CPU == PPC603) || (CPU == PPCEC603))
|
|
#include <arch/ppc/ppc603.h>
|
|
#endif /* ((CPU == PPC603) || (CPU == PPCEC603)) */
|
|
|
|
#if (CPU == PPC85XX)
|
|
#include <arch/ppc/ppc85xx.h>
|
|
#endif /* CPU == PPC85XX */
|
|
|
|
#if (CPU == PPC604)
|
|
#include <arch/ppc/ppc604.h>
|
|
#endif /* CPU == PPC604) */
|
|
|
|
#if (CPU == PPC860)
|
|
#include <arch/ppc/ppc860.h>
|
|
#endif /* CPU == PPC860) */
|
|
|
|
#if (CPU == PPC970)
|
|
#include <arch/ppc/ppc970.h>
|
|
#endif /* CPU == PPC970 */
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
/*
|
|
* Use constant size if known (when building for a specific CPU type)
|
|
* else fetch from a global variable (when building for generic PPC32)
|
|
*/
|
|
#undef _CACHE_ALIGN_SIZE
|
|
#ifdef _CPU_CACHE_ALIGN_SIZE
|
|
#define _CACHE_ALIGN_SIZE _CPU_CACHE_ALIGN_SIZE
|
|
#else /* _CPU_CACHE_ALIGN_SIZE */
|
|
# ifndef _ASMLANGUAGE
|
|
# define _CACHE_ALIGN_SIZE _ppcCacheLineSize
|
|
extern int _ppcCacheLineSize;
|
|
# endif /* _ASMLANGUAGE */
|
|
#endif /* _CPU_CACHE_ALIGN_SIZE */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#include <arch/ppc/archPpcCommon.h>
|
|
|
|
#include <arch/ppc/toolPpc.h>
|
|
|
|
/*
|
|
* VX_OBJ_ALIGN_SIZE is the default allocation boundary for kernel objects.
|
|
* This is used for both statically and dynamically allocated objects.
|
|
*/
|
|
|
|
#define VX_OBJ_ALIGN_SIZE 8
|
|
|
|
#endif /* __INCarchPpch */
|