104 lines
3.0 KiB
C
104 lines
3.0 KiB
C
/* stm32f2xx.h - SOC specific header file */
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/*
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* Copyright (c) 2012 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01c,02jul12,rec fix USART base addresses
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01b,02may12,rec Moved to hwif/soc. Split into lower level files.
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01a,21mar12,jmz Created
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*/
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/*
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DESCRIPTION
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This file contains register definitions specifc to the stm32f2xxx series SOC.
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SEE ALSO:
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\tb RM0033 Reference manual - STM32F205xx, STM32F207xx, STM32F215xx and STM32F217xx
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advanced ARM-based 32-bit MCUs
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*/
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#ifndef __INCstm32f2xxh
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#define __INCstm32f2xxh
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* macros to manipulate registers */
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#define STM32F2XX_REG_READ(address) \
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*(volatile UINT32 *)(address)
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#define STM32F2XX_REG_WRITE(address, value) \
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*(volatile UINT32 *)(address) = (UINT32)(value)
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#define STM32F2XX_SHORT_REG_WRITE(address, value) \
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*(volatile UINT16*)(address) = value
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#define STM32F2XX_SHORT_REG_READ(address) \
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(*(volatile UINT16*)(address))
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/* Region allocation for General-purpose I/O (GPIO) registers */
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#define STM32F2XX_GPIO_BASE 0x40020000
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/* Region allocation for Reset and Clock Control (RCC) registers */
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#define STM32F2XX_RCC_BASE 0x40023800
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/* Region allocation for Flash Memory Interface (FMI) registers */
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#define STM32F2XX_FMI_BASE 0x40023C00
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/* Region allocation for Flexible Static Memory Controller (FSMC) registers */
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#define STM32F2XX_FSMC_BASE 0xA0000000
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/*
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* Region allocation for Universal Synchronous Asynchronous Receiver Transmitter
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* (USART) registers
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*/
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#define STM32F2XX_USART1_BASE 0x40011000
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#define STM32F2XX_USART2_BASE 0x40004400
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#define STM32F2XX_USART3_BASE 0x40004800
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#define STM32F2XX_UART4_BASE 0x40004C00
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#define STM32F2XX_UART5_BASE 0x40005000
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#define STM32F2XX_USART6_BASE 0x40011400
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/* Region allocation for General Purpose Timer (GPT) registers */
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#define STM32F2XX_TIM1_BASE 0x40001000
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#define STM32F2XX_TIM2_BASE 0x40000000
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#define STM32F2XX_TIM3_BASE 0x40000400
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#define STM32F2XX_TIM4_BASE 0x40000800
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#define STM32F2XX_TIM5_BASE 0x40000C00
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#define STM32F2XX_TIM6_BASE 0x40001000
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#define STM32F2XX_TIM7_BASE 0x40001400
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#define STM32F2XX_TIM8_BASE 0x40010400
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#define STM32F2XX_TIM9_BASE 0x40014000
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#define STM32F2XX_TIM10_BASE 0x40014400
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#define STM32F2XX_TIM11_BASE 0x40014800
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#define STM32F2XX_TIM12_BASE 0x40001800
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#define STM32F2XX_TIM13_BASE 0x40001C00
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#define STM32F2XX_TIM14_BASE 0x40002000
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/* Region allocation for Ethernet Driver registers */
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#define STM32F2XX_ETH_BASE 0x40028000
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCstm32f2xxh */
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