152 lines
5.8 KiB
C
152 lines
5.8 KiB
C
/* vsbchip2.h - VSBchip2 Interface Controller */
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/* Copyright 1994-1996 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01b,15nov96,dat fixed SPR 4046, offset for VSBCHIP2_PTR was corrected.
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01a,16feb94,dzb written.
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*/
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/*
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DESCRIPTION
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This file contains constants for the VSBchip2 interface controller.
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*/
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#ifdef DOC
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#define __INCvsbchip2h
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#endif /* DOC */
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#ifndef __INCvsbchip2h
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#define __INCvsbchip2h
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef _ASMLANGUAGE
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#define CAST
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#define CAST_US
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#define CAST_UL
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#else
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#define CAST (char *)
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#define CAST_US (unsigned short *)
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#define CAST_UL (unsigned long *)
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#endif /* _ASMLANGUAGE */
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#ifndef VSBCHIP2_BASE_ADRS
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#define VSBCHIP2_BASE_ADRS 0xfff41000
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#endif /* VSBCHIP2_BASE_ADRS */
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#ifndef VSBCHIP2_REG_INTERVAL
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#define VSBCHIP2_REG_INTERVAL 1
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#endif /* VSBCHIP2_REG_INTERVAL */
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#ifndef VSB_ADRS
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#define VSB_ADRS(reg) (CAST VSBCHIP2_BASE_ADRS + (reg * VSBCHIP2_REG_INTERVAL))
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#endif /* VSB_ADRS */
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#ifndef VSB_ADRS_US
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#define VSB_ADRS_US(reg) (CAST_US VSB_ADRS(reg))
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#endif /* VSB_ADRS_US */
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#ifndef VSB_ADRS_UL
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#define VSB_ADRS_UL(reg) (CAST_UL VSB_ADRS(reg))
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#endif /* VSB_ADRS_UL */
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/**********************************/
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/* VSBCHIP2 register locations: */
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/**********************************/
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#define VSBCHIP2_CCCSR VSB_ADRS_US (0x000) /* Chip Control/Status Reg */
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#define VSBCHIP2_LIVBR VSB_ADRS_US (0x002) /* Local Int Vector Base Reg */
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#define VSBCHIP2_LISR VSB_ADRS_US (0x004) /* Local Interrupt Status Reg */
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#define VSBCHIP2_LIER VSB_ADRS_US (0x006) /* Local Interrupt Enable Reg */
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#define VSBCHIP2_LILR VSB_ADRS_UL (0x008) /* Local Interrupt Level Reg */
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#define VSBCHIP2_VRCSR VSB_ADRS_US (0x010) /* VSB Req Control/Status Reg */
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#define VSBCHIP2_TCR VSB_ADRS_US (0x014) /* Timer Control Register */
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#define VSBCHIP2_TCPR VSB_ADRS_US (0x016) /* Timer Clock Prescale Reg */
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#define VSBCHIP2_LS1ARR VSB_ADRS_UL (0x018) /* Local Bus Slave Addr Reg 1 */
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#define VSBCHIP2_LS1AOR VSB_ADRS_US (0x01c) /* Local Bus Slave Off Reg 1 */
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#define VSBCHIP2_LS1AR VSB_ADRS_US (0x01e) /* Local Bus Slave Attr Reg 1 */
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#define VSBCHIP2_LS2ARR VSB_ADRS_UL (0x020) /* Local Bus Slave Addr Reg 2 */
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#define VSBCHIP2_LS2AOR VSB_ADRS_US (0x024) /* Local Bus Slave Off Reg 2 */
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#define VSBCHIP2_LS2AR VSB_ADRS_US (0x026) /* Local Bus Slave Attr Reg 2 */
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#define VSBCHIP2_LS3ARR VSB_ADRS_UL (0x028) /* Local Bus Slave Addr Reg 3 */
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#define VSBCHIP2_LS3AOR VSB_ADRS_US (0x02c) /* Local Bus Slave Off Reg 3 */
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#define VSBCHIP2_LS3AR VSB_ADRS_US (0x02e) /* Local Bus Slave Attr Reg 3 */
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#define VSBCHIP2_LS4ARR VSB_ADRS_UL (0x030) /* Local Bus Slave Addr Reg 4 */
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#define VSBCHIP2_LS4AOR VSB_ADRS_US (0x034) /* Local Bus Slave Off Reg 4 */
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#define VSBCHIP2_LS4AR VSB_ADRS_US (0x036) /* Local Bus Slave Attr Reg 4 */
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#define VSBCHIP2_LEAR VSB_ADRS_UL (0x074) /* Local Error Address Reg */
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#define VSBCHIP2_PCCR VSB_ADRS_UL (0x078) /* Prescaler Current Cnt Reg */
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#define VSBCHIP2_PTR VSB_ADRS_UL (0x07C) /* Prescaler Test Register */
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#define VSBCHIP2_EAR VSB_ADRS_UL (0x100) /* EVSB Attention Register */
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#define VSBCHIP2_ETASR VSB_ADRS_UL (0x104) /* EVSB Test-And-Set Reg */
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#define VSBCHIP2_GPR1 VSB_ADRS_UL (0x108) /* General Purpose Reg 1 */
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#define VSBCHIP2_GPR2 VSB_ADRS_UL (0x10c) /* General Purpose Reg 2 */
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#define VSBCHIP2_VESR VSB_ADRS_UL (0x110) /* VSB Error Status Register */
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#define VSBCHIP2_VICR VSB_ADRS (0x114) /* VSB Interrupt Control Reg */
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#define VSBCHIP2_VIVR VSB_ADRS (0x115) /* VSB Interrupt Vector Reg */
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#define VSBCHIP2_VIER VSB_ADRS (0x116) /* VSB Interrupt Enable Reg */
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#define VSBCHIP2_VISR VSB_ADRS (0x117) /* VSB Interrupt Status Reg */
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#define VSBCHIP2_VS1ARR VSB_ADRS_UL (0x118) /* VSB Slave Addr Range Reg 1 */
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#define VSBCHIP2_VS1AOR VSB_ADRS_US (0x11c) /* VSB Slave Addr Off Reg 1 */
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#define VSBCHIP2_VS1AR VSB_ADRS_US (0x11e) /* VSB Slave Attribute Reg 1 */
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#define VSBCHIP2_VS2ARR VSB_ADRS_UL (0x120) /* VSB Slave Addr Range Reg 2 */
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#define VSBCHIP2_VS2AOR VSB_ADRS_US (0x124) /* VSB Slave Addr Off Reg 2 */
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#define VSBCHIP2_VS2AR VSB_ADRS_US (0x126) /* VSB Slave Attribute Reg 2 */
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/**********************************/
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/* VSBCHIP2 register definitions: */
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/**********************************/
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/* VSBCHIP2_VRCSR register definitions: */
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#define VRCSR_LVRWD 0x0100 /* release when done */
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/* VSBCHIP2_VTCR register definitions: */
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#define VTCR_VARBTD 0x1000 /* VSB arbitration timer disable */
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#define VTCR_VATS_32MS 0x0800 /* VSB access timer select (32 msecs) */
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#define VTCR_VATS_DIS 0x0c00 /* VSB access timer select (32 msecs) */
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#define VTCR_VTXS_256US 0x0200 /* VSB transfer timer select (256 usecs) */
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#define VTCR_VTXS_DIS 0x0300 /* VSB transfer timer select disabled */
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/* VSBCHIP2_LS1AR register definitions: */
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#define LS1AR_REN 0x8000 /* read enable (when set, read access) */
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#define LS1AR_WEN 0x4000 /* write enable (when set, write access) */
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#define LS1AR_WPE 0x0800 /* write post enable */
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#define LS1AR_BNCEN 0x0080 /* bounce mode enable */
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#define LS1AR_VSP1 0x0020
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#define LS1AR_VSP0 0x0010
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/* VSBCHIP2_VS1AR register definitions: */
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#define VS1AR_REN 0x8000 /* read enable (when set, read access) */
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#define VS1AR_WEN 0x4000 /* write enable (when set, write access) */
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#define VS1AR_POR 0x2000 /* participate on read */
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#define VS1AR_POW 0x1000 /* participate on write */
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#define VS1AR_WPE 0x0800 /* write post enable */
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#define VS1AR_SAS 0x0400 /* system address space */
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#define VS1AR_ALTAS 0x0200 /* alternate address space */
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#define VS1AR_IOAS 0x0100 /* I/O address space */
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#define VS1AR_LOCK 0x0040 /* lock local bus on block transfers */
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#define VS1AR_LBTS1 0x0008
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#define VS1AR_LBTS0 0x0004
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#define VS1AR_LBSC1 0x0002
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#define VS1AR_LBSC0 0x0001
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCvsbchip2h */
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