155 lines
5.3 KiB
C
155 lines
5.3 KiB
C
/* i8250Sio.h - header file for binary interface Intel 8250 UART driver */
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/* Copyright 1984-1993, 2010 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01e,29apr10,pad Moved extern C statement after include statements.
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01d,03jun98,hdn changed I8250_IIR_MASK from 6 to 7 to fix the TX-int problem.
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01c,22may97,db added macros for all i8250 registers(SPR #7542).
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01b,15jun95,ms updated for new driver.
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01a,15mar95,myz written (from i8250Serial.h)
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*/
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#ifndef __INCi8250Sioh
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#define __INCi8250Sioh
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#ifndef _ASMLANGUAGE
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#include "vxWorks.h"
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#include "sioLib.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* channel data structure */
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typedef struct /* I8250_CHAN */
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{
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SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */
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STATUS (*getTxChar) (); /* pointer to xmitr function */
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STATUS (*putRcvChar) (); /* pointer tp rcvr function */
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void * getTxArg;
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void * putRcvArg;
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UINT16 int_vec; /* interrupt vector number */
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UINT16 channelMode; /* SIO_MODE_[INT | POLL] */
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UCHAR (*inByte) (int); /* routine to read a byte from register */
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void (*outByte)(int,char); /* routine to write a byte to register */
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ULONG lcr; /* UART line control register */
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ULONG lst; /* UART line status register */
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ULONG mdc; /* UART modem control register */
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ULONG msr; /* UART modem status register */
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ULONG ier; /* UART interrupt enable register */
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ULONG iid; /* UART interrupt ID register */
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ULONG brdl; /* UART baud rate register */
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ULONG brdh; /* UART baud rate register */
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ULONG data; /* UART data register */
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ULONG options; /* UART hardware options */
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} I8250_CHAN;
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typedef struct /* BAUD */
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{
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int rate; /* a baud rate */
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int preset; /* counter preset value to write to DUSCC_CTPR[HL]A */
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} BAUD;
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/* register definitions */
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#define UART_THR 0x00 /* Transmitter holding reg. */
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#define UART_RDR 0x00 /* Receiver data reg. */
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#define UART_BRDL 0x00 /* Baud rate divisor (LSB) */
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#define UART_BRDH 0x01 /* Baud rate divisor (MSB) */
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#define UART_IER 0x01 /* Interrupt enable reg. */
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#define UART_IID 0x02 /* Interrupt ID reg. */
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#define UART_LCR 0x03 /* Line control reg. */
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#define UART_MDC 0x04 /* Modem control reg. */
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#define UART_LST 0x05 /* Line status reg. */
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#define UART_MSR 0x06 /* Modem status reg. */
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/* equates for interrupt enable register */
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#define I8250_IER_RXRDY 0x01 /* receiver data ready */
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#define I8250_IER_TBE 0x02 /* transmit bit enable */
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#define I8250_IER_LST 0x04 /* line status interrupts */
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#define I8250_IER_MSI 0x08 /* modem status interrupts */
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/* equates for interrupt identification register */
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#define I8250_IIR_IP 0x01 /* interrupt pending bit */
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#define I8250_IIR_MASK 0x07 /* interrupt id bits mask */
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#define I8250_IIR_MSTAT 0x00 /* modem status interrupt */
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#define I8250_IIR_THRE 0X02 /* transmit holding register empty */
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#define I8250_IIR_RBRF 0x04 /* receiver buffer register full */
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#define I8250_IIR_SEOB 0x06 /* serialization error or break */
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/* equates for line control register */
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#define I8250_LCR_CS5 0x00 /* 5 bits data size */
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#define I8250_LCR_CS6 0x01 /* 6 bits data size */
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#define I8250_LCR_CS7 0x02 /* 7 bits data size */
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#define I8250_LCR_CS8 0x03 /* 8 bits data size */
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#define I8250_LCR_2_STB 0x04 /* 2 stop bits */
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#define I8250_LCR_1_STB 0x00 /* 1 stop bit */
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#define I8250_LCR_PEN 0x08 /* parity enable */
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#define I8250_LCR_PDIS 0x00 /* parity disable */
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#define I8250_LCR_EPS 0x10 /* even parity slect */
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#define I8250_LCR_SP 0x20 /* stick parity select */
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#define I8250_LCR_SBRK 0x40 /* break control bit */
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#define I8250_LCR_DLAB 0x80 /* divisor latch access enable */
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/* equates for the modem control register */
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#define I8250_MCR_DTR 0x01 /* dtr output */
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#define I8250_MCR_RTS 0x02 /* rts output */
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#define I8250_MCR_OUT1 0x04 /* output #1 */
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#define I8250_MCR_OUT2 0x08 /* output #2 */
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#define I8250_MCR_LOOP 0x10 /* loop back */
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/* equates for line status register */
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#define I8250_LSR_RXRDY 0x01 /* receiver data available */
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#define I8250_LSR_OE 0x02 /* overrun error */
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#define I8250_LSR_PE 0x04 /* parity error */
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#define I8250_LSR_FE 0x08 /* framing error */
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#define I8250_LSR_BI 0x10 /* break interrupt */
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#define I8250_LSR_THRE 0x20 /* transmit holding register empty */
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#define I8250_LSR_TEMT 0x40 /* transmitter empty */
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/* equates for modem status register */
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#define I8250_MSR_DCTS 0x01 /* cts change */
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#define I8250_MSR_DDSR 0x02 /* dsr change */
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#define I8250_MSR_DRI 0x04 /* ring change */
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#define I8250_MSR_DDCD 0x08 /* data carrier change */
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#define I8250_MSR_CTS 0x10 /* complement of cts */
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#define I8250_MSR_DSR 0x20 /* complement of dsr */
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#define I8250_MSR_RI 0x40 /* complement of ring signal */
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#define I8250_MSR_DCD 0x80 /* complement of dcd */
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#if defined(__STDC__) || defined(__cplusplus)
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extern void i8250HrdInit(I8250_CHAN *pDev);
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extern void i8250Int (I8250_CHAN *pDev);
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#else
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extern void i8250HrdInit();
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extern void i8250Int();
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#endif /* __STDC__ */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCi8250h */
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