518 lines
17 KiB
C
518 lines
17 KiB
C
/* m8260SccEnd.h - Motorola MPC8260 Serial Communication Controllers (SCC) Ethernet interface header */
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/*
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* Copyright (c) 1996-2009 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01e,28jan09,wap Complete driver rewrite (WIND00146685)
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01d,16jan03,gjc SPR#85071 and SPR#85093 :Added define to support DUPLEX.
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01c,17may02,gjc #SPR 75922, undef SCC_BUF if prev defined.
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01b,09may02,gjc Fixing SPR #75046 by setting SCC to Full Duplex Mode.
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01a,10may01,g_h adapted from sbcM8260CpmEnd.h (ver. 01b).
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*/
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#ifndef __INCm8260SccEndh
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#define __INCm8260SccEndh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define ETHER_ADDR_LEN 6
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#define ETHER_CRC_LEN 4
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typedef struct endNetPool
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{
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NET_POOL pool;
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void * pMblkMemArea;
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void * pClMemArea;
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} END_NET_POOL;
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#define sccEndPoolTupleFree(x) netMblkClChainFree(x)
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#define sccEndPoolTupleGet(x) \
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netTupleGet((x), (x)->clTbl[0]->clSize, M_DONTWAIT, MT_DATA, 0)
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#define SCC_GSMR_L 0x00 /* SCC General Mode */
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#define SCC_GSMR_H 0x04 /* SCC General Mode */
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#define SCC_PSMR 0x08 /* SCC Proto. Spec */
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#define SCC_TODR 0x0C /* SCC Tx On Demand */
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#define SCC_DSR 0x0E /* SCC Data Sync */
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#define SCC_SCCER 0x10 /* SCC Event Reg */
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#define SCC_SCCMR 0x14 /* SCC Mask Reg */
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#define SCC_SCCSR 0x17 /* SCC Status Reg */
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#define SCC_GSMRL_HDLC 0x00000000 /* HDLC mode */
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#define SCC_GSMRL_APPLETALK 0x00000002 /* AppleTalk mode (LocalTalk) */
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#define SCC_GSMRL_SS7 0x00000003 /* SS7 mode (microcode) */
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#define SCC_GSMRL_UART 0x00000004 /* UART mode */
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#define SCC_GSMRL_PROFI_BUS 0x00000005 /* Profi-Bus mode (microcode) */
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#define SCC_GSMRL_ASYNC_HDLC 0x00000006 /* async HDLC mode (microcode)*/
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#define SCC_GSMRL_V14 0x00000007 /* V.14 mode */
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#define SCC_GSMRL_BISYNC 0x00000008 /* BISYNC mode */
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#define SCC_GSMRL_DDCMP 0x00000009 /* DDCMP mode (microcode) */
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#define SCC_GSMRL_ETHERNET 0x0000000c /* ethernet mode (SCC1 only) */
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#define SCC_GSMRL_ENT 0x00000010 /* enable transmitter */
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#define SCC_GSMRL_ENR 0x00000020 /* enable receiver */
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#define SCC_GSMRL_LOOPBACK 0x00000040 /* local loopback mode */
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#define SCC_GSMRL_ECHO 0x00000080 /* automatic echo mode */
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#define SCC_GSMRL_TENC 0x00000700 /* transmitter encoding method*/
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#define SCC_GSMRL_RENC 0x00003800 /* receiver encoding method */
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#define SCC_GSMRL_RDCR_X8 0x00004000 /* receive DPLL clock x8 */
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#define SCC_GSMRL_RDCR_X16 0x00008000 /* receive DPLL clock x16 */
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#define SCC_GSMRL_RDCR_X32 0x0000c000 /* receive DPLL clock x32 */
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#define SCC_GSMRL_TDCR_X8 0x00010000 /* transmit DPLL clock x8 */
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#define SCC_GSMRL_TDCR_X16 0x00020000 /* transmit DPLL clock x16 */
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#define SCC_GSMRL_TDCR_X32 0x00030000 /* transmit DPLL clock x32 */
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#define SCC_GSMRL_TEND 0x00040000 /* transmitter frame ending */
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#define SCC_GSMRL_TPP_00 0x00180000 /* Tx preamble pattern = 00 */
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#define SCC_GSMRL_TPP_10 0x00080000 /* Tx preamble pattern = 10 */
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#define SCC_GSMRL_TPP_01 0x00100000 /* Tx preamble pattern = 01 */
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#define SCC_GSMRL_TPP_11 0x00180000 /* Tx preamble pattern = 11 */
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#define SCC_GSMRL_TPL_NONE 0x00000000 /* no Tx preamble (default) */
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#define SCC_GSMRL_TPL_8 0x00200000 /* Tx preamble = 1 byte */
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#define SCC_GSMRL_TPL_16 0x00400000 /* Tx preamble = 2 bytes */
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#define SCC_GSMRL_TPL_32 0x00600000 /* Tx preamble = 4 bytes */
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#define SCC_GSMRL_TPL_48 0x00800000 /* Tx preamble = 6 bytes */
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#define SCC_GSMRL_TPL_64 0x00a00000 /* Tx preamble = 8 bytes */
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#define SCC_GSMRL_TPL_128 0x00c00000 /* Tx preamble = 16 bytes */
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#define SCC_GSMRL_TINV 0x01000000 /* DPLL transmit input invert */
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#define SCC_GSMRL_RINV 0x02000000 /* DPLL receive input invert */
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#define SCC_GSMRL_TSNC 0x0c000000 /* transmit sense */
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#define SCC_GSMRL_TCI 0x10000000 /* transmit clock invert */
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#define SCC_GSMRL_EDGE 0x60000000 /* adjustment edge +/- */
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#define SCC_GSMRH_RSYN 0x00000001 /* receive sync timing*/
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#define SCC_GSMRH_RTSM 0x00000002 /* RTS* mode */
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#define SCC_GSMRH_SYNL 0x0000000c /* sync length */
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#define SCC_GSMRH_TXSY 0x00000010 /* transmitter/receiver sync */
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#define SCC_GSMRH_RFW 0x00000020 /* Rx FIFO width */
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#define SCC_GSMRH_TFL 0x00000040 /* transmit FIFO length */
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#define SCC_GSMRH_CTSS 0x00000080 /* CTS* sampling */
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#define SCC_GSMRH_CDS 0x00000100 /* CD* sampling */
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#define SCC_GSMRH_CTSP 0x00000200 /* CTS* pulse */
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#define SCC_GSMRH_CDP 0x00000400 /* CD* pulse */
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#define SCC_GSMRH_TTX 0x00000800 /* transparent transmitter */
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#define SCC_GSMRH_TRX 0x00001000 /* transparent receiver */
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#define SCC_GSMRH_REVD 0x00002000 /* reverse data */
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#define SCC_GSMRH_TCRC 0x0000c000 /* transparent CRC */
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#define SCC_GSMRH_GDE 0x00010000 /* glitch detect enable */
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/* CPM - Communication Processor Module */
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/* SCC Ethernet Protocol Specific Mode Register definitions */
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#define SCC_ETHER_PSMR_FDE 0x0001
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#define SCC_ETHER_PSMR_NIB_13 0x0000 /* SFD 13 bits after TENA */
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#define SCC_ETHER_PSMR_NIB_14 0x0002 /* SFD 14 bits after TENA */
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#define SCC_ETHER_PSMR_NIB_15 0x0004 /* SFD 15 bits after TENA */
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#define SCC_ETHER_PSMR_NIB_16 0x0006 /* SFD 16 bits after TENA */
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#define SCC_ETHER_PSMR_NIB_21 0x0008 /* SFD 21 bits after TENA */
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#define SCC_ETHER_PSMR_NIB_22 0x000a /* SFD 22 bits after TENA */
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#define SCC_ETHER_PSMR_NIB_23 0x000c /* SFD 23 bits after TENA */
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#define SCC_ETHER_PSMR_NIB_24 0x000e /* SFD 24 bits after TENA */
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#define SCC_ETHER_PSMR_LCW 0x0010 /* late collision window */
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#define SCC_ETHER_PSMR_SIP 0x0200 /* sample input pins */
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#define SCC_ETHER_PSMR_LPB 0x0040 /* loopback operation */
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#define SCC_ETHER_PSMR_SBT 0x0080 /* stop backoff timer */
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#define SCC_ETHER_PSMR_BRO 0x0100 /* broadcast address */
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#define SCC_ETHER_PSMR_PRO 0x0200 /* promiscuous mode */
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#define SCC_ETHER_PSMR_CRC 0x0800 /* CRC selection */
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#define SCC_ETHER_PSMR_IAM 0x1000 /* individual address mode */
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#define SCC_ETHER_PSMR_RSH 0x2000 /* receive short frame */
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#define SCC_ETHER_PSMR_FC 0x4000 /* force collision */
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#define SCC_ETHER_PSMR_HBC 0x8000 /* heartbeat checking*/
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/* SCC Ethernet Event and Mask Register definitions */
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#define SCC_ETHER_SCCX_RXB 0x0001 /* buffer received event */
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#define SCC_ETHER_SCCX_TXB 0x0002 /* buffer transmitted event */
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#define SCC_ETHER_SCCX_BSY 0x0004 /* busy condition */
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#define SCC_ETHER_SCCX_RXF 0x0008 /* frame received event */
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#define SCC_ETHER_SCCX_TXE 0x0010 /* transmission error event */
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#define SCC_ETHER_SCCX_GRA 0x0080 /* graceful stop event */
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/* SCC Ethernet Receive Buffer Descriptor definitions */
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#define SCC_ETHER_RX_BD_CL 0x0001 /* collision condition */
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#define SCC_ETHER_RX_BD_OV 0x0002 /* overrun condition */
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#define SCC_ETHER_RX_BD_CR 0x0004 /* Rx CRC error */
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#define SCC_ETHER_RX_BD_SH 0x0008 /* short frame received */
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#define SCC_ETHER_RX_BD_NO 0x0010 /* Rx nonoctet aligned frame */
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#define SCC_ETHER_RX_BD_LG 0x0020 /* Rx frame length violation */
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#define SCC_ETHER_RX_BD_M 0x0100 /* miss bit for prom mode */
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#define SCC_ETHER_RX_BD_F 0x0400 /* buffer is first in frame */
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#define SCC_ETHER_RX_BD_L 0x0800 /* buffer is last in frame */
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#define SCC_ETHER_RX_BD_I 0x1000 /* interrupt on receive */
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#define SCC_ETHER_RX_BD_W 0x2000 /* last BD in ring */
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#define SCC_ETHER_RX_BD_E 0x8000 /* buffer is empty */
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/* SCC Ethernet Transmit Buffer Descriptor definitions */
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#define SCC_ETHER_TX_BD_CSL 0x0001 /* carrier sense lost */
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#define SCC_ETHER_TX_BD_UN 0x0002 /* underrun */
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#define SCC_ETHER_TX_BD_RC 0x003c /* retry count */
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#define SCC_ETHER_TX_BD_RL 0x0040 /* retransmission limit */
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#define SCC_ETHER_TX_BD_LC 0x0080 /* late collision */
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#define SCC_ETHER_TX_BD_HB 0x0100 /* heartbeat */
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#define SCC_ETHER_TX_BD_DEF 0x0200 /* defer indication */
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#define SCC_ETHER_TX_BD_TC 0x0400 /* auto transmit CRC */
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#define SCC_ETHER_TX_BD_L 0x0800 /* buffer is last in frame */
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#define SCC_ETHER_TX_BD_I 0x1000 /* interrupt on transmit */
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#define SCC_ETHER_TX_BD_W 0x2000 /* last BD in ring */
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#define SCC_ETHER_TX_BD_PAD 0x4000 /* auto pad short frames */
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#define SCC_ETHER_TX_BD_R 0x8000 /* buffer is ready */
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/* SCC Parameter RAM registers in ethernet mode */
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#define SCC_RBASE 0x00
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#define SCC_TBASE 0x02
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#define SCC_RFCR 0x04
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#define SCC_TFCR 0x05
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#define SCC_MRBLR 0x06
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#define SCC_RSTATE 0x08
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#define SCC_RIP 0x0C
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#define SCC_RBPTR 0x10
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#define SCC_RCOUNT 0x12
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#define SCC_RTEMP 0x14
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#define SCC_TSTATE 0x18
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#define SCC_TIP 0x1C
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#define SCC_TBPTR 0x20
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#define SCC_TCOUNT 0x22
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#define SCC_TTEMP 0x24
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#define SCC_RCRC 0x28
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#define SCC_TCRC 0x2C
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#define SCC_C_PRES 0x30
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#define SCC_C_MASK 0x34
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#define SCC_CRCEC 0x38
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#define SCC_ALEC 0x3C
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#define SCC_DISFC 0x40
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#define SCC_PADS 0x44
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#define SCC_RET_LIM 0x46
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#define SCC_RET_CNT 0x48
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#define SCC_MFLR 0x4A
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#define SCC_MINFLR 0x4C
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#define SCC_MAXD1 0x4E
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#define SCC_MAXD2 0x50
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#define SCC_MAXD 0x52
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#define SCC_DMA_CNT 0x54
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#define SCC_MAX_B 0x56
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#define SCC_GADDR1 0x58
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#define SCC_GADDR2 0x5A
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#define SCC_GADDR3 0x5C
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#define SCC_GADDR4 0x5E
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#define SCC_TBUF0_DATA0 0x60
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#define SCC_TBUF0_DATA1 0x64
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#define SCC_TBUF0_RBA0 0x68
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#define SCC_TBUF0_CRC 0x6C
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#define SCC_TBUF0_BCNT 0x80
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#define SCC_PADDR_H 0x72
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#define SCC_PADDR_M 0x74
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#define SCC_PADDR_L 0x7C
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#define SCC_P_PER 0x78
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#define SCC_RFBD_PTR 0x7A
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#define SCC_TFBD_PTR 0x7C
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#define SCC_TLBD_PTR 0x7E
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#define SCC_TBUF1_DATA0 0x80
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#define SCC_TBUF1_DATA1 0x84
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#define SCC_TBUF1_RBA0 0x88
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#define SCC_TBUF1_CRC 0x8C
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#define SCC_TBUF1_BCNT 0x90
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#define SCC_TX_LEN 0x92
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#define SCC_IADDR1 0x94
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#define SCC_IADDR2 0x96
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#define SCC_IADDR3 0x98
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#define SCC_IADDR4 0x9A
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#define SCC_BOFF_CNT 0x9C
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#define SCC_TADDR_H 0x9E
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#define SCC_TADDR_M 0xA0
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#define SCC_TADDR_L 0xA2
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/* RFCR and TFCR registers */
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#define FCR_DTB 0x02
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#define FCR_TC2 0x04
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#define FCR_BO_LE 0x08
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#define FCR_BO_BE 0x10
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#define FCR_GBL 0x20
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#define SCC_NAME "motscc"
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#define SCC_TIMEOUT 10000
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#define SCC_INTRS \
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(SCC_ETHER_SCCX_RXB|SCC_ETHER_SCCX_BSY|SCC_ETHER_SCCX_RXF| \
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SCC_ETHER_SCCX_TXB|SCC_ETHER_SCCX_TXE)
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#define SCC_RXINTRS \
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(SCC_ETHER_SCCX_RXB|SCC_ETHER_SCCX_BSY|SCC_ETHER_SCCX_RXF)
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#define SCC_TXINTRS \
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(SCC_ETHER_SCCX_TXB|SCC_ETHER_SCCX_TXE)
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#define SCC_LINKINTRS 0
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#define SCC_RBD_ALIGN 16
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#define SCC_ALIGN(x) (char *)(((UINT32)(x) + (15 * 2)) & ~15)
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#define SCC_ADJ(x) \
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(x)->m_data = SCC_ALIGN((x)->m_data)
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#define SCC_CLSIZE 1600
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#define SCC_INC_DESC(x, y) (x) = ((x + 1) & (y - 1))
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#define SCC_MAXFRAG 16
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#define SCC_MAX_RX 16
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/*
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* We deliberately specify a large number of DMA descriptors here,
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* in order to avoid losing any frames on receive. The number of
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* buffers (SCC_BUF_CNT) should be at least twice the number of
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* RX descriptors (SCC_RX_DESC_CNT), plus the number of TX descriptors
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* (SCC_TX_DESC_CNT).
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*
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* Note that unlike the FEC and FCC interfaces, the DMA descriptor
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* rings for the CPM/SCC must reside in DPRAM. Normally, the range
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* from 0x2000 to 0x21FF is used, howeve this is very small and only
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* allows for 32 descriptors for RX and TX. The MPC860/MPC850 has
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* additional DPRAM located at 0x3000 through 0x3BFF. We use this
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* region instead, so that we can have a fairly large RX ring.
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*/
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#define SCC_BUF_CNT (256)
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#define SCC_RX_DESC_CNT 32
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#define SCC_TX_DESC_CNT 32
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#define SCC_RX_DPRAM 0x3000
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#define SCC_TX_DPRAM 0x3400
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/*
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#define SCC_BUF_CNT 768
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#define SCC_RX_DESC_CNT 256
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#define SCC_TX_DESC_CNT 128
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#define SCC_RX_DPRAM 0x3000
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#define SCC_TX_DPRAM 0x3800
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*/
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typedef struct scc_desc
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{
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volatile UINT16 bdSts;
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volatile UINT16 bdLen;
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volatile UINT32 bdAddr;
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} SCC_DESC;
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/*
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* Private adapter context structure.
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*/
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typedef struct scc_drv_ctrl
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{
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END_OBJ sccEndObj;
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void * sccPram;
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void * sccIram;
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int sccUnit;
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int sccIvec;
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int sccIlevel;
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volatile BOOL sccIntPending;
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volatile BOOL sccRxPending;
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volatile BOOL sccTxPending;
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UINT8 sccTxCur;
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UINT8 sccTxLast;
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volatile BOOL sccTxStall;
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UINT16 sccTxThresh;
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BOOL sccPolling;
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M_BLK_ID sccPollBuf;
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UINT16 sccIntMask;
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UINT8 sccAddr[ETHER_ADDR_LEN + 2];
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SCC_DESC *sccRxDescMem;
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SCC_DESC *sccTxDescMem;
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M_BLK_ID sccRxMblk[SCC_RX_DESC_CNT];
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M_BLK_ID sccTxMblk[SCC_TX_DESC_CNT];
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UINT32 sccTxProd;
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UINT32 sccTxCons;
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UINT32 sccTxFree;
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UINT32 sccRxIdx;
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int sccNum;
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END_ERR sccLastError;
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} SCC_DRV_CTRL;
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#ifndef BSP_VERSION
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LOCAL UINT32 csr_read_4 (SCC_DRV_CTRL *, UINT32, int);
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LOCAL void csr_write_4 (SCC_DRV_CTRL *, UINT32, int, UINT32);
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LOCAL UINT16 csr_read_2 (SCC_DRV_CTRL *, UINT16, int);
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LOCAL void csr_write_2 (SCC_DRV_CTRL *, UINT16, int, UINT16);
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#ifdef notused
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LOCAL UINT8 csr_read_1 (SCC_DRV_CTRL *, UINT8, int);
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#endif
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LOCAL void csr_write_1 (SCC_DRV_CTRL *, UINT8, int, UINT8);
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#define SCC_PRAM 0
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#define SCC_IRAM 1
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LOCAL UINT32 csr_read_4
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(
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SCC_DRV_CTRL * pDrv,
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UINT32 addr,
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int ix
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)
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{
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UINT32 data;
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if (ix == SCC_PRAM)
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data = *(UINT32 *)((UINT8 *)pDrv->sccPram + addr);
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else
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data = *(UINT32 *)((UINT8 *)pDrv->sccIram + addr);
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return (data);
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}
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LOCAL void csr_write_4
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(
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SCC_DRV_CTRL * pDrv,
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UINT32 addr,
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int ix,
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UINT32 data
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)
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{
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UINT32 * reg;
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if (ix == SCC_PRAM)
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reg = (UINT32 *)((UINT8 *)pDrv->sccPram + addr);
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else
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reg = (UINT32 *)((UINT8 *)pDrv->sccIram + addr);
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*reg = data;
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return;
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}
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LOCAL UINT16 csr_read_2
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(
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SCC_DRV_CTRL * pDrv,
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UINT16 addr,
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int ix
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)
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{
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UINT16 data;
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if (ix == SCC_PRAM)
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data = *(UINT16 *)((UINT8 *)pDrv->sccPram + addr);
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else
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data = *(UINT16 *)((UINT8 *)pDrv->sccIram + addr);
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return (data);
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}
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LOCAL void csr_write_2
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(
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SCC_DRV_CTRL * pDrv,
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UINT16 addr,
|
|
int ix,
|
|
UINT16 data
|
|
)
|
|
{
|
|
UINT16 * reg;
|
|
|
|
if (ix == SCC_PRAM)
|
|
reg = (UINT16 *)((UINT8 *)pDrv->sccPram + addr);
|
|
else
|
|
reg = (UINT16 *)((UINT8 *)pDrv->sccIram + addr);
|
|
*reg = data;
|
|
return;
|
|
}
|
|
|
|
#ifdef notused
|
|
LOCAL UINT8 csr_read_1
|
|
(
|
|
SCC_DRV_CTRL * pDrv,
|
|
UINT8 addr,
|
|
int ix
|
|
)
|
|
{
|
|
UINT16 data;
|
|
if (ix == SCC_PRAM)
|
|
data = *(UINT8 *)((UINT8 *)pDrv->sccPram + addr);
|
|
else
|
|
data = *(UINT8 *)((UINT8 *)pDrv->sccIram + addr);
|
|
return (data);
|
|
}
|
|
#endif
|
|
|
|
LOCAL void csr_write_1
|
|
(
|
|
SCC_DRV_CTRL * pDrv,
|
|
UINT8 addr,
|
|
int ix,
|
|
UINT8 data
|
|
)
|
|
{
|
|
UINT8 * reg;
|
|
|
|
if (ix == SCC_PRAM)
|
|
reg = (UINT8 *)((UINT8 *)pDrv->sccPram + addr);
|
|
else
|
|
reg = (UINT8 *)((UINT8 *)pDrv->sccIram + addr);
|
|
*reg = data;
|
|
return;
|
|
}
|
|
|
|
#define CSR_READ_4 csr_read_4
|
|
#define CSR_READ_2 csr_read_2
|
|
#define CSR_READ_1 csr_read_1
|
|
#define CSR_WRITE_4 csr_write_4
|
|
#define CSR_WRITE_2 csr_write_2
|
|
#define CSR_WRITE_1 csr_write_1
|
|
|
|
#define CSR_SETBIT_1(pDev, offset, ix, val) \
|
|
CSR_WRITE_1(pDev, offset, ix, CSR_READ_1(pDev, offset, ix) | (val))
|
|
|
|
#define CSR_CLRBIT_1(pDev, offset, ix, val) \
|
|
CSR_WRITE_1(pDev, offset, CSR_READ_1(pDev, offset, ix) & ~(val))
|
|
|
|
#define CSR_SETBIT_2(pDev, offset, ix, val) \
|
|
CSR_WRITE_2(pDev, offset, ix, CSR_READ_2(pDev, offset, ix) | (val))
|
|
|
|
#define CSR_CLRBIT_2(pDev, offset, ix, val) \
|
|
CSR_WRITE_2(pDev, offset, ix, CSR_READ_2(pDev, offset, ix) & ~(val))
|
|
|
|
#define CSR_SETBIT_4(pDev, offset, ix, val) \
|
|
CSR_WRITE_4(pDev, offset, ix, CSR_READ_4(pDev, offset, ix) | (val))
|
|
|
|
#define CSR_CLRBIT_4(pDev, offset, ix, val) \
|
|
CSR_WRITE_4(pDev, offset, ix, CSR_READ_4(pDev, offset, ix) & ~(val))
|
|
|
|
#endif /* BSP_VERSION */
|
|
|
|
/*
|
|
* Note: these have no meaning for this driver. They're provided only
|
|
* for backwards compatibility with some BSPs, which expect these flags
|
|
* to be defined.
|
|
*/
|
|
|
|
#define SCC_USR_RUNNING_FROM_ROM 0x00000001 /* inhibit zcopy mode */
|
|
#define SCC_USR_DUPLEX_HALF 0x00000000 /* Half duplex */
|
|
#define SCC_USR_DUPLEX_FULL 0x00000002 /* Full duplex */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __INCm8260SccEndh */
|