182 lines
7.5 KiB
C
182 lines
7.5 KiB
C
/* mpc107Dma.h - MPC107 DMA registers definitions */
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/* Copyright 1984-2000, 2010 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01c,29apr10,pad Moved extern C statement after include statements.
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01b,11sep00,rcs fix include path for mpc107.h
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01a,06jun00,bri written
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*/
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#ifndef __INCmpc107Dmah
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#define __INCmpc107Dmah
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/* includes */
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#include "drv/multi/mpc107.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* defines */
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/* MPC107 configuration registers for DMA interface */
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#define MPC107_DMA_EUMBBAR 0x1000 /* Offset of DMA registers */
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/* in EUMBBAR Space */
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/* DMA Channel Zero Register Definitions */
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#define MPC107_DMA_DMR0 (MPC107_DMA_EUMBBAR + 0x100)/* Mode Register */
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#define MPC107_DMA_DSR0 (MPC107_DMA_EUMBBAR + 0x104)/* Status Register */
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#define MPC107_DMA_CDAR0 (MPC107_DMA_EUMBBAR + 0x108)/* Current Descriptor */
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#define MPC107_DMA_SAR0 (MPC107_DMA_EUMBBAR + 0x110)/* Source Address */
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#define MPC107_DMA_DAR0 (MPC107_DMA_EUMBBAR + 0x118)/* Destination Address */
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#define MPC107_DMA_BCR0 (MPC107_DMA_EUMBBAR + 0x120)/* Byte Count */
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#define MPC107_DMA_NDAR0 (MPC107_DMA_EUMBBAR + 0x124)/* Next Descriptor */
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/* DMA Channel One Register Definitions */
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#define MPC107_DMA_DMR1 (MPC107_DMA_EUMBBAR + 0x200) /* Mode Register */
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#define MPC107_DMA_DSR1 (MPC107_DMA_EUMBBAR + 0x204) /* Status Register */
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#define MPC107_DMA_CDAR1 (MPC107_DMA_EUMBBAR + 0x208) /* Current Descriptor */
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#define MPC107_DMA_SAR1 (MPC107_DMA_EUMBBAR + 0x210) /* Source Address */
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#define MPC107_DMA_DAR1 (MPC107_DMA_EUMBBAR + 0x218) /* Destination Address */
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#define MPC107_DMA_BCR1 (MPC107_DMA_EUMBBAR + 0x220) /* Byte Count */
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#define MPC107_DMA_NDAR1 (MPC107_DMA_EUMBBAR + 0x224) /* Next Descriptor */
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/* Bit Definitions */
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/* Mode Register Bit Definitons */
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#define MPC107_DMA_DMR_CS 0x00000001 /* Channel Start */
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#define MPC107_DMA_DMR_CC 0x00000002 /* Channel Continue */
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#define MPC107_DMA_DMR_CTM 0x00000004 /* Direct DMA mode */
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/* Channel Transfer */
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#define MPC107_DMA_DMR_DL 0x00000008 /* Descriptor Location */
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#define MPC107_DMA_DMR_EOTIE 0x00000080 /* End of Transfer */
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/* Interrupt Enable */
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#define MPC107_DMA_DMR_EIE 0x00000100 /* Error Interrupt Enable */
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#define MPC107_DMA_DMR_PDE 0x00040000 /* Periodic DMA Enable */
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/* Status Register Bit Definitions */
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#define MPC107_DMA_DSR_EOCAI 0x00000001 /* End of chain or */
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/* direct Interrupt */
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#define MPC107_DMA_DSR_EOSI 0x00000002 /* End of Segment Interrupt */
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#define MPC107_DMA_DSR_CB 0x00000004 /* Channel Busy */
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#define MPC107_DMA_DSR_PE 0x00000010 /* PCI Error */
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#define MPC107_DMA_DSR_LME 0x00000080 /* Local Memory Error */
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/* Current Descriptor Address Register Bit definitions */
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#define MPC107_DMA_CDAR_CTT_SHIFT 0x2 /* Transfer Type Shift */
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#define MPC107_DMA_CDAR_ADDR_MASK 0xffffffc0 /* Address Mask */
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#define MPC107_DMA_CDAR_EOSIE 0x00000008 /* End of Segment Interrupt */
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#define MPC107_DMA_CDAR_SNEN 0x00000010 /* Snoop Enable */
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/* Next Descriptor Address Register Bit definitions */
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#define MPC107_DMA_NDAR_EOTD 0x00000001 /* End of transfer descriptor */
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#define MPC107_DMA_NDAR_NDEOSIE 0x00000008 /* Next descriptor */
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/* end-of-segment interrupt */
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/* enable */
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#define MPC107_DMA_NDAR_NDSNEN 0x00000010 /* Snoop Enable */
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#define MPC107_DMA_NDAR_ADDR_MASK 0xffffffc0 /* Address Mask */
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/*
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* DMA 0 Mode register default value
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* Error Interrupt Disabled ,End of Transfer
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* Interrupt Disabled and Direct Mode DMA transfer
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*/
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#define MPC107_DMA_DMR0_DEFAULT 0x04
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/*
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* DMA 1 Mode register default value
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* Error Interrupt Disabled ,End of Transfer
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* Interrupt Disabled and Direct Mode DMA transfer
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*/
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#define MPC107_DMA_DMR1_DEFAULT 0x04
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/* General Definitions */
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#define MPC107_DMA_CHANNEL0 0x0 /* Channel Zero */
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#define MPC107_DMA_CHANNEL1 0x1 /* Channel One */
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#define MPC107_DMA_MEM_ALIGN 0x3 /* For aligining to 8 words */
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/* 2exp3 = 8 */
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#define MPC107_DMA_CH_BUSY_MASK 0x00000001 /* Channel busy mask */
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#define MPC107_DMA_TIMEOUT_BUSY 0x10000
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/* Error Numbers and Return Values */
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#define MPC107_DMA_PERIODIC_CH 0x01 /* Channel configured for */
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/* Periodic DMA */
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#define MPC107_DMA_CHAIN_CH 0x02 /* Channel configured for */
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/* Chained DMA */
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#define MPC107_DMA_DIRECT_CH 0x03 /* Channel configured for */
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/* Direct DMA */
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#define MPC107_DMA_PERIODIC_CH_FREE 0x04 /* periodic DMA is configured */
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/* and channel is free */
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#define MPC107_DMA_PERIODIC_CH_BUSY 0x05 /* "periodic" DMA is configured */
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/* and channel is Busy */
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#define MPC107_DMA_CHAIN_CH_FREE 0x06 /* chained DMA is configured */
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/* and channel is free */
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#define MPC107_DMA_CHAIN_CH_BUSY 0x07 /* chained DMA is configured */
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/* and channel is busy */
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#define MPC107_DMA_DIRECT_CH_FREE 0x08 /* direct DMA is configured */
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/* and channel is free */
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#define MPC107_DMA_DIRECT_CH_BUSY 0x09 /* direct DMA is configured */
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/* and channel is busy */
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#define MPC107_DMA_NUM_BYTES 0x0a /* Number of bytes is zero */
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#define MPC107_DMA_UNDEF_CH 0x0b /* Undefined Channel Number */
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/* typedefs */
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/*
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* Descriptors for Chained /Periodic DMA transfers .
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* Descriptors should be alligned on a 8 word byte boundary
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*/
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typedef struct mpc107DmaDescriptors
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{
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UCHAR *pSourceAddress; /* Pointer to Source address */
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ULONG reserved1; /* Reserved 1 */
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UCHAR *pDestinationAddress; /* Pointer to Destination address */
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ULONG reserved2; /* Reserved 2 */
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struct mpc107DmaDescriptors *pNextDescriptorAddress; /* Pointer to next */
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/* descriptor */
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ULONG reserved3; /* Reserved 3 */
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ULONG numberOfBytes; /* Number of bytes */
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ULONG reserved4; /* Reserved 4 */
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} MPC107_DMA_DESCRIPTOR;
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/* function declrations */
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IMPORT void mpc107DmaInit (void);
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IMPORT STATUS mpc107DmaStartDirect (UINT32 channelNumber, UINT32 transferType,
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UINT32 sourceAddress ,
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UINT32 destinationAddress,
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UINT32 numberOfBytes);
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IMPORT STATUS mpc107DmaChainedStart (UINT32 channelNumber,UINT32 timePeriod);
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IMPORT STATUS mpc107DmaPeriodicStop (UINT32 channelNumber );
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IMPORT STATUS mpc107DmaBuildDecsriptor (UINT32 channelNumber,
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UCHAR *pSourceAddress,
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UCHAR *pDestinationAddress,
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UINT32 transferType,
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UINT32 numberOfBytes);
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IMPORT INT32 mpc107DmaStatus (ULONG channel);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCmpc107Dmah */
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