439 lines
14 KiB
C
439 lines
14 KiB
C
/* vxAtomicArchLib.h - x86_64 IA32 specific atomic library header */
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/*
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* Copyright (c) 2006-2008, 2010, 2018 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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modification history
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--------------------
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19sep18,m_w make sure the code map of inline ASM under GNU
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is correct (VXW6-86665)
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13sep10,scm WIND002322578 remove type-punning warnings...
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29apr10,pad Moved extern C statement after include statements.
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23mar10,scm add inline gnu routines for 64 bit
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23mar10,scm add fixed size APIs, made memory barriers available in user space
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16jun08,zl use _WRS_BARRIER() for memory barrier implementations.
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17jan08,gls renamed inline routines
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03jan08,gls fixed DCC _inline_vxCas()
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11dec07,gls Added _inline_vxCas()
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29nov06,scm Created
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*/
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#ifndef __INCvxAtomicArchLibh
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#define __INCvxAtomicArchLibh
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#include <arch/i86/x86_64/vxAtomicArchLibCommon.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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#if defined (__DCC__)
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#define vxCas_inline vxAtomicCas
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#define vxAtomicCas_inline vxAtomicCas
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#define vxAtomic64Cas_inline vxAtomic64Cas
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#define vxAtomic32Cas_inline vxAtomic32Cas
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#define vxAtomicAdd_inline vxAtomicAdd
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#define vxAtomic64Add_inline vxAtomic64Add
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#define vxAtomic32Add_inline vxAtomic32Add
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#define vxAtomicSub_inline vxAtomicSub
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#define vxAtomic64Sub_inline vxAtomic64Sub
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#define vxAtomic32Sub_inline vxAtomic32Sub
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#define vxAtomicInc_inline vxAtomicInc
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#define vxAtomic64Inc_inline vxAtomic64Inc
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#define vxAtomic32Inc_inline vxAtomic32Inc
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#define vxAtomicDec_inline vxAtomicDec
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#define vxAtomic64Dec_inline vxAtomic64Dec
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#define vxAtomic32Dec_inline vxAtomic32Dec
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#define vxAtomicGet_inline vxAtomicGet
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#define vxAtomic64Get_inline vxAtomic64Get
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#define vxAtomic32Get_inline vxAtomic32Get
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#define vxAtomicSet_inline vxAtomicSet
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#define vxAtomic64Set_inline vxAtomic64Set
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#define vxAtomic32Set_inline vxAtomic32Set
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#define vxAtomicClear_inline vxAtomicClear
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#define vxAtomic64Clear_inline vxAtomic64Clear
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#define vxAtomic32Clear_inline vxAtomic32Clear
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#elif defined (__GNUC__)
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static __inline__ BOOL vxAtomic64Cas_inline
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(
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atomic64_t * target, /* memory location to compare-and-swap */
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atomic64Val_t oldValue, /* compare to this value */
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atomic64Val_t newValue /* swap with this value */
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)
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{
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BOOL swapped;
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__asm__ volatile
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(
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"movq %3, %%rax;" /* move oldValue to %rax */
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"lock;" /* lock the Bus during the next inst */
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"cmpxchgq %4, %2;" /* if (%rax == *target) */
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/* {ZF = 1; *target = newValue;} */
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/* else */
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/* {ZF = 0; %rax = *target;} */
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"setz %%al;" /* if success, set swapped to TRUE else FALSE */
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"movzb %%al, %0" /* zero extend swapped */
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: "=&a" (swapped), /* output: swapped is %0 */
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"=m" (target) /* target is %1 */
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: "m" (*(target)), /* input: *target is %2 */
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"g" (oldValue), /* oldValue is %3 */
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"r" (newValue) /* newValue is %4 */
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: "memory" /* memory clobber for code barrier */
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);
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return swapped;
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}
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static __inline__ BOOL vxAtomic32Cas_inline
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(
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atomic32_t * target, /* memory location to compare-and-swap */
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atomic32Val_t oldValue, /* compare to this value */
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atomic32Val_t newValue /* swap with this value */
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)
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{
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BOOL swapped;
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__asm__ volatile
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(
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"movl %3, %%eax;" /* move oldValue to %eax */
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"lock;" /* lock the Bus during the next inst */
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"cmpxchgl %4, %2;" /* if (%eax == *target) */
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/* {ZF = 1; *target = newValue;} */
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/* else */
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/* {ZF = 0; %eax = *target;} */
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"setz %%al;" /* if success, set swapped to TRUE else FALSE */
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"movzbl %%al, %0" /* zero extend swapped */
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: "=&a" (swapped), /* output: swapped is %0 */
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"=m" (target) /* target is %1 */
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: "m" (*(target)), /* input: *target is %2 */
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"g" (oldValue), /* oldValue is %3 */
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"r" (newValue) /* newValue is %4 */
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: "memory" /* memory clobber for code barrier */
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);
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return swapped;
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}
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static __inline__ atomic64Val_t vxAtomic64Add_inline
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(
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atomic64_t * target,
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atomic64Val_t value
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)
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{
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__asm__ volatile
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(
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"lock;" /* lock the Bus during the next inst */
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"xaddq %0, %2" /* TMP = value + *target */
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/* value = *target */
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/* *target = TMP */
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: "+r" (value), /* output: value is %0 */
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"=m" (target) /* target is %1 */
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: "m" (*(target)) /* input: *target is %2 */
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: "memory" /* memory clobber for code barrier */
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);
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return value;
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}
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static __inline__ atomic32Val_t vxAtomic32Add_inline
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(
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atomic32_t * target,
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atomic32Val_t value
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)
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{
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__asm__ volatile
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(
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"lock;" /* lock the Bus during the next inst */
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"xaddl %0, %2" /* TMP = value + *target */
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/* value = *target */
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/* *target = TMP */
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: "+r" (value), /* output: value is %0 */
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"=m" (target) /* target is %1 */
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: "m" (*(target)) /* input: *target is %2 */
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: "memory" /* memory clobber for code barrier */
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);
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return value;
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}
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static __inline__ atomic64Val_t vxAtomic64Sub_inline
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(
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atomic64_t * target,
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atomic64Val_t value
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)
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{
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__asm__ volatile
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(
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"negq %0;" /* Negate value... */
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"lock;" /* lock the Bus during the next inst */
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"xaddq %0, %2" /* TMP = -value + *target */
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/* value = *target */
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/* *target = TMP */
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: "+r" (value), /* output: value is %0 */
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"=m" (target) /* target is %1 */
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: "m" (*(target)) /* input: *target is %2 */
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: "memory" /* memory clobber for code barrier */
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);
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return value;
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}
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static __inline__ atomic32Val_t vxAtomic32Sub_inline
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(
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atomic32_t * target,
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atomic32Val_t value
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)
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{
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__asm__ volatile
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(
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"negl %0;" /* Negate value... */
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"lock;" /* lock the Bus during the next inst */
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"xaddl %0, %2" /* TMP = -value + *target */
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/* value = *target */
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/* *target = TMP */
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: "+r" (value), /* output: value is %0 */
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"=m" (target) /* target is %1 */
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: "m" (*(target)) /* input: *target is %2 */
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: "memory" /* memory clobber for code barrier */
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);
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return value;
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}
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static __inline__ atomic64Val_t vxAtomic64Inc_inline
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(
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atomic64_t * target
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)
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{
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atomic64Val_t value;
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__asm__ volatile
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(
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"movq $1, %0;" /* inc by 1 */
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"lock;" /* lock the Bus during the next inst */
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"xaddq %0, %2" /* TMP = *target + 1 */
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/* value = *target */
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/* *target = TMP */
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: "=&r" (value), /* output: value is %0 */
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"=m" (target) /* target is %1 */
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: "m" (*(target)) /* input: *target is %2 */
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: "memory" /* memory clobber for code barrier */
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);
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return value;
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}
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static __inline__ atomic32Val_t vxAtomic32Inc_inline
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(
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atomic32_t * target
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)
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{
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atomic32Val_t value;
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__asm__ volatile
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(
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"movl $1, %0;" /* inc by 1 */
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"lock;" /* lock the Bus during the next inst */
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"xaddl %0, %2" /* TMP = *target + 1 */
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/* value = *target */
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/* *target = TMP */
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: "=&r" (value), /* output: value is %0 */
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"=m" (target) /* target is %1 */
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: "m" (*(target)) /* input: *target is %2 */
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: "memory" /* memory clobber for code barrier */
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);
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return value;
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}
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static __inline__ atomic64Val_t vxAtomic64Dec_inline
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(
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atomic64_t * target
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)
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{
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atomic64Val_t value;
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__asm__ volatile
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(
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"movq $(-1), %0;" /* dec by 1 */
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"lock;" /* lock the Bus during the next inst */
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"xaddq %0, %2" /* TMP = *target - 1 */
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/* value = *target */
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/* *target = TMP */
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: "=&r" (value), /* output: value is %0 */
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"=m" (target) /* target is %1 */
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: "m" (*(target)) /* input: *target is %2 */
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: "memory" /* memory clobber for code barrier */
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);
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return value;
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}
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static __inline__ atomic32Val_t vxAtomic32Dec_inline
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(
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atomic32_t * target
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)
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{
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atomic32Val_t value;
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__asm__ volatile
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(
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"movl $(-1), %0;" /* dec by 1 */
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"lock;" /* lock the Bus during the next inst */
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"xaddl %0, %2" /* TMP = *target - 1 */
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/* value = *target */
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/* *target = TMP */
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: "=&r" (value), /* output: value is %0 */
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"=m" (target) /* target is %1 */
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: "m" (*(target)) /* input: *target is %2 */
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: "memory" /* memory clobber for code barrier */
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);
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return value;
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}
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static __inline__ atomic64Val_t vxAtomic64Get_inline
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(
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atomic64_t * target
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)
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{
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atomic64Val_t value;
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__asm__ volatile
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(
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"movq %1, %0" /* get value with bus-lock */
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: "=r" (value) /* output: value is %0 */
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: "m" (*(target)) /* input: *target is %1 */
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: "memory" /* memory clobber for code barrier */
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);
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return value;
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}
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static __inline__ atomic32Val_t vxAtomic32Get_inline
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(
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atomic32_t * target
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)
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{
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atomic32Val_t value;
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__asm__ volatile
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(
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"movl %1, %0" /* get value with bus-lock */
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: "=r" (value) /* output: value is %0 */
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: "m" (*(target)) /* input: *target is %1 */
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: "memory" /* memory clobber for code barrier */
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);
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return value;
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}
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static __inline__ atomic64Val_t vxAtomic64Set_inline
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(
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atomic64_t * target,
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atomic64Val_t value
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)
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{
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__asm__ volatile
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(
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"xchgq %0, %2" /* set value with bus-lock */
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: "+r" (value), /* output: value is %0 */
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"=m" (target) /* target is %1 */
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: "m" (*(target)) /* input: *target is %2 */
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: "memory" /* memory clobber for code barrier */
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);
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return value;
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}
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static __inline__ atomic32Val_t vxAtomic32Set_inline
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(
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atomic32_t * target,
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atomic32Val_t value
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)
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{
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__asm__ volatile
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(
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"xchgl %0, %2" /* set value with bus-lock */
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: "+r" (value), /* output: value is %0 */
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"=m" (target) /* target is %1 */
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: "m" (*(target)) /* input: *target is %2 */
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: "memory" /* memory clobber for code barrier */
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);
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return value;
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}
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static __inline__ atomic64Val_t vxAtomic64Clear_inline
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(
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atomic64_t * target
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)
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{
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atomic64Val_t value;
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__asm__ volatile
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(
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"movq $0, %0;" /* 'clear' value to set */
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"xchgq %0, %2" /* swap 'clear' value with bus-lock */
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: "=&r" (value), /* output: value is %0 */
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"=m" (target) /* target is %1 */
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: "m" (*(target)) /* input: *target is %2 */
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: "memory" /* memory clobber for code barrier */
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);
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return value;
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}
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static __inline__ atomic32Val_t vxAtomic32Clear_inline
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(
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atomic32_t * target
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)
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{
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atomic32Val_t value;
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__asm__ volatile
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(
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"movl $0, %0;" /* 'clear' value to set */
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"xchgl %0, %2" /* swap 'clear' value with bus-lock */
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: "=&r" (value), /* output: value is %0 */
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"=m" (target) /* target is %1 */
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: "m" (*(target)) /* input: *target is %2 */
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: "memory" /* memory clobber for code barrier */
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);
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return value;
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}
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#define vxCas_inline vxAtomic64Cas_inline
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#define vxAtomicCas_inline vxAtomic64Cas_inline
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#define vxAtomicAdd_inline vxAtomic64Add_inline
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#define vxAtomicSub_inline vxAtomic64Sub_inline
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#define vxAtomicInc_inline vxAtomic64Inc_inline
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#define vxAtomicDec_inline vxAtomic64Dec_inline
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#define vxAtomicGet_inline vxAtomic64Get_inline
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#define vxAtomicSet_inline vxAtomic64Set_inline
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#define vxAtomicClear_inline vxAtomic64Clear_inline
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#else
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#define vxCas_inline vxAtomicCas
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#define vxAtomicCas_inline vxAtomicCas
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#define vxAtomic64Cas_inline vxAtomic64Cas
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#define vxAtomic32Cas_inline vxAtomic32Cas
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#define vxAtomicAdd_inline vxAtomicAdd
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#define vxAtomic64Add_inline vxAtomic64Add
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#define vxAtomic32Add_inline vxAtomic32Add
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#define vxAtomicSub_inline vxAtomicSub
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#define vxAtomic64Sub_inline vxAtomic64Sub
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#define vxAtomic32Sub_inline vxAtomic32Sub
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#define vxAtomicInc_inline vxAtomicInc
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#define vxAtomic64Inc_inline vxAtomic64Inc
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#define vxAtomic32Inc_inline vxAtomic32Inc
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#define vxAtomicDec_inline vxAtomicDec
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#define vxAtomic64Dec_inline vxAtomic64Dec
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#define vxAtomic32Dec_inline vxAtomic32Dec
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#define vxAtomicGet_inline vxAtomicGet
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#define vxAtomic64Get_inline vxAtomic64Get
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#define vxAtomic32Get_inline vxAtomic32Get
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#define vxAtomicSet_inline vxAtomicSet
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#define vxAtomic64Set_inline vxAtomic64Set
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#define vxAtomic32Set_inline vxAtomic32Set
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#define vxAtomicClear_inline vxAtomicClear
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#define vxAtomic64Clear_inline vxAtomic64Clear
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#define vxAtomic32Clear_inline vxAtomic32Clear
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#endif /* _VX_TOOL_FAMILY */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCvxAtomicArchLibh */
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