373 lines
11 KiB
C
373 lines
11 KiB
C
/* dbgStrLib.h - Debug Store mechanism definitions header file */
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/*
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* Copyright 2001, 2009-2010 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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modification history
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--------------------
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01c,29apr10,pad Moved extern C statement after include statements.
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01b,24feb09,jb Update to 64-bits
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01a,23jul01,hdn written
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*/
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#ifndef __INCdbgStrLibh
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#define __INCdbgStrLibh
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#include "arch/i86/regsP7.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* DS buffer : BTS/PEBS minimum/default/threshold size */
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#define BTS_NBYTES_MIN 0x1000 /* 4KB minimum BTS buffer */
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#define BTS_NBYTES_DEF 0x4000 /* 16KB default BTS buffer */
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#define BTS_NBYTES_OFF 0x200 /* .5KB (max - threshold) BTS */
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#define PEBS_NBYTES_MIN 0x1000 /* 4KB minimum PEBS buffer */
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#define PEBS_NBYTES_DEF 0x4000 /* 16KB default PEBS buffer */
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#define PEBS_NBYTES_OFF 0x200 /* .5KB (max - threshold) PEBS */
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#define PEBS_DEF_RESET -1LL /* default reset counter value */
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/* BTS : record bit */
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#define BTS_PREDICTED 0x00000010 /* bit4: Branch Predicted */
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/* PEBS : events */
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#define PEBS_FRONT_END 0x01
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#define PEBS_EXECUTION 0x02
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#define PEBS_REPLAY 0x03
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/* PEBS : metrics (Front End Event) */
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#define PEBS_MEMORY_LOADS 0x01
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#define PEBS_MEMORY_STORES 0x02
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/* PEBS : metrics (Execution Event) */
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#define PEBS_PACKED_SP 0x03
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#define PEBS_PACKED_DP 0x04
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#define PEBS_SCALAR_SP 0x05
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#define PEBS_SCALAR_DP 0x06
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#define PEBS_128BIT_MMX 0x07
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#define PEBS_64BIT_MMX 0x08
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#define PEBS_X87_FP 0x09
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#define PEBS_X87_SIMD_MOVES 0x0a
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/* PEBS : metrics (Replay Event) */
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#define PEBS_1STL_CACHE_LOAD_MISS 0x0b
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#define PEBS_2NDL_CACHE_LOAD_MISS 0x0c
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#define PEBS_DTLB_LOAD_MISS 0x0d
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#define PEBS_DTLB_STORE_MISS 0x0e
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#define PEBS_DTLB_ALL_MISS 0x0f
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#define PEBS_MOB_LOAD_REPLAY 0x10
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#define PEBS_SPLIT_LOAD 0x11
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#define PEBS_SPLIT_STORE 0x12
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/* PEBS : ESCR, CCCR definitions (Front End Event) */
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#define ESCR_FRONT_END \
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(((0x08 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
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((DS_BIT_1 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
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ESCR_TAG_ENABLE)
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#define CCCR_FRONT_END \
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(((0x05 << DS_SHIFT_13) & CCCR_ESCR_SELECT) | \
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CCCR_RSVD)
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#define ESCR_MEMORY_LOADS \
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(((0x02 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
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((DS_BIT_1 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
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ESCR_TAG_ENABLE)
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#define ESCR_MEMORY_STORES \
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(((0x02 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
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((DS_BIT_2 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
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ESCR_TAG_ENABLE)
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/* PEBS : ESCR, CCCR definitions (Execution Event) */
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#define ESCR_EXECUTION \
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(((0x0c << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
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((DS_BIT_0 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
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((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
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ESCR_TAG_ENABLE)
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#define CCCR_EXECUTION \
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(((0x05 << DS_SHIFT_13) & CCCR_ESCR_SELECT) | \
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CCCR_RSVD)
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#define ESCR_PACKED_SP \
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(((0x08 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
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((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
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((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
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ESCR_TAG_ENABLE)
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#define ESCR_PACKED_DP \
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(((0x0c << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
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((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
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((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
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ESCR_TAG_ENABLE)
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#define ESCR_SCALAR_SP \
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(((0x0a << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
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((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
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((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
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ESCR_TAG_ENABLE)
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#define ESCR_SCALAR_DP \
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(((0x0e << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
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((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
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((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
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ESCR_TAG_ENABLE)
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#define ESCR_64BIT_MMX \
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(((0x02 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
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((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
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((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
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ESCR_TAG_ENABLE)
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#define ESCR_128BIT_MMX \
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(((0x1a << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
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((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
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((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
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ESCR_TAG_ENABLE)
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#define ESCR_X87_FP \
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(((0x04 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
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((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
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((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
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ESCR_TAG_ENABLE)
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#define ESCR_X87_SIMD_MOVES \
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(((0x2e << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
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(((DS_BIT_3 | DS_BIT_4) << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
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((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
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ESCR_TAG_ENABLE)
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/* PEBS : ESCR, CCCR definitions (Replay Event) */
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#define ESCR_REPLAY \
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(((0x09 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
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((DS_BIT_0 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
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((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
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ESCR_TAG_ENABLE)
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#define CCCR_REPLAY \
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(((0x05 << DS_SHIFT_13) & CCCR_ESCR_SELECT) | \
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CCCR_RSVD)
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#define ESCR_MOB_LOAD_REPLAY \
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(((0x03 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
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(((DS_BIT_4 | DS_BIT_5) << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
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ESCR_TAG_ENABLE)
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#define ESCR_SPLIT_LOAD \
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(((0x04 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
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((DS_BIT_1 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
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ESCR_TAG_ENABLE)
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#define ESCR_SPLIT_STORE \
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(((0x05 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
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((DS_BIT_1 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
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ESCR_TAG_ENABLE)
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/* DS : MSR(ESCR) bit definition */
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#define DS_BIT_0 0x00000001
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#define DS_BIT_1 0x00000002
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#define DS_BIT_2 0x00000004
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#define DS_BIT_3 0x00000008
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#define DS_BIT_4 0x00000010
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#define DS_BIT_5 0x00000020
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#define DS_BIT_6 0x00000040
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#define DS_BIT_7 0x00000080
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#define DS_BIT_8 0x00000100
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#define DS_BIT_9 0x00000200
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#define DS_BIT_10 0x00000400
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#define DS_BIT_11 0x00000800
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#define DS_BIT_12 0x00001000
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#define DS_BIT_13 0x00002000
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#define DS_BIT_14 0x00004000
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#define DS_BIT_15 0x00008000
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#define DS_BIT_16 0x00010000
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#define DS_BIT_17 0x00020000
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#define DS_BIT_18 0x00040000
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#define DS_BIT_19 0x00080000
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#define DS_BIT_20 0x00100000
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#define DS_BIT_21 0x00200000
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#define DS_BIT_22 0x00400000
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#define DS_BIT_23 0x00800000
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#define DS_BIT_24 0x01000000
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#define DS_BIT_25 0x02000000
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#define DS_BIT_26 0x04000000
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#define DS_BIT_27 0x08000000
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#define DS_BIT_28 0x10000000
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#define DS_BIT_29 0x20000000
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#define DS_BIT_30 0x40000000
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#define DS_BIT_31 0x80000000
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/* DS : MSR(ESCR, CCCR) shift count definition */
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#define DS_SHIFT_1 1
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#define DS_SHIFT_2 2
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#define DS_SHIFT_3 3
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#define DS_SHIFT_4 4
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#define DS_SHIFT_5 5
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#define DS_SHIFT_6 6
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#define DS_SHIFT_7 7
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#define DS_SHIFT_8 8
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#define DS_SHIFT_9 9
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#define DS_SHIFT_10 10
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#define DS_SHIFT_11 11
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#define DS_SHIFT_12 12
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#define DS_SHIFT_13 13
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#define DS_SHIFT_14 14
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#define DS_SHIFT_15 15
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#define DS_SHIFT_16 16
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#define DS_SHIFT_17 17
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#define DS_SHIFT_18 18
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#define DS_SHIFT_19 19
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#define DS_SHIFT_20 20
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#define DS_SHIFT_21 21
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#define DS_SHIFT_22 22
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#define DS_SHIFT_23 23
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#define DS_SHIFT_24 24
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#define DS_SHIFT_25 25
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#define DS_SHIFT_26 26
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#define DS_SHIFT_27 27
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#define DS_SHIFT_28 28
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#define DS_SHIFT_29 29
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#define DS_SHIFT_30 30
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#define DS_SHIFT_31 31
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#ifndef _ASMLANGUAGE
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typedef struct btsRec /* BTS (Branch Trace Store) record */
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{
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ULONG pcFm; /* Last Branch From */
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ULONG pcTo; /* Last Branch To */
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ULONG misc; /* bit4: Branch Predicted */
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} BTS_REC;
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typedef struct pebsRec /* PEBS (Precise Event Based Sampling) rec */
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{
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ULONG eflags; /* EFLAGS */
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ULONG rip; /* Linear IP */
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ULONG r15; /* R15 */
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ULONG r14; /* R14 */
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ULONG r13; /* R13 */
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ULONG r12; /* R12 */
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ULONG r11; /* R11 */
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ULONG r10; /* R10 */
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ULONG r9; /* R9 */
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ULONG r8; /* R8 */
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ULONG rax; /* RAX */
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ULONG rbx; /* RBX */
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ULONG rcx; /* RCX */
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ULONG rdx; /* RDX */
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ULONG rsi; /* RSI */
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ULONG rdi; /* RDI */
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ULONG rbp; /* RBP */
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ULONG rsp; /* RSP */
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} PEBS_REC;
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typedef struct dsBufHeader /* DS (Debug Store) buffer management */
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{
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BTS_REC * btsBase; /* BTS buffer base */
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BTS_REC * btsIndex; /* BTS index */
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UINT32 btsMax; /* BTS absolute maximum */
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UINT32 btsThreshold; /* BTS interrupt threshold */
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PEBS_REC * pebsBase; /* PEBS buffer base */
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PEBS_REC * pebsIndex; /* PEBS index */
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UINT32 pebsMax; /* PEBS absolute maximum */
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UINT32 pebsThreshold; /* PEBS interrupt threshold */
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LL_INT pebsCtr; /* PEBS counter reset value */
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UINT32 reserved[3]; /* reserved */
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} DS_BUF_HEADER;
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typedef struct dsConfig /* DS (Debug Store) configuration */
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{
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UINT32 btsNbytes; /* BTS buffer size */
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BOOL btsAvailable; /* TRUE if BTS is available */
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BOOL btsEnabled; /* TRUE if BTS is enabled */
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BOOL btsIntMode; /* TRUE for interrupt mode */
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BOOL btsBufMode; /* TRUE to store BTMs */
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UINT32 pebsNbytes; /* PEBS buffer size */
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BOOL pebsAvailable; /* TRUE if PEBS is available */
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BOOL pebsEnabled; /* TRUE if PEBS is enabled */
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INT32 pebsEvent; /* PEBS event */
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INT32 pebsMetric; /* PEBS metric */
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BOOL pebsOs; /* PEBS os */
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LL_INT pebsCtr; /* PEBS counter */
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DS_BUF_HEADER * pH; /* DS buffer header */
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} DS_CONFIG;
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/* function declarations */
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#if defined(__STDC__) || defined(__cplusplus)
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extern STATUS dbgStrLibInit (UINT32 nBytesBts, UINT32 nBytesPebs,
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BOOL sysMode);
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extern DS_BUF_HEADER * dbgStrBufInit (DS_BUF_HEADER * pH,
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BTS_REC * btsBufAddr,
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UINT32 btsMaxOffset,
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UINT32 btsIntOffset,
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PEBS_REC * pebsBufAddr,
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UINT32 pebsMaxOffset,
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UINT32 pebsIntOffset);
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extern STATUS dbgStrBufAlloc (WIND_TCB * pTcb);
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extern STATUS dbgStrBufFree (WIND_TCB * pTcb);
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extern STATUS dbgStrConfig (WIND_TCB * pTcb,
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BOOL btsEnable, BOOL pebsEnable,
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BOOL btsIntMode, BOOL btsBufMode,
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INT32 pebsEvent, INT32 pebsMetric,
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BOOL pebsOs, LL_INT * pPebsValue);
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extern STATUS dbgStrStart (WIND_TCB * pTcb);
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extern STATUS dbgStrStop (WIND_TCB * pTcb);
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extern STATUS dbgStrBtsModeSet (BOOL intMode, BOOL bufMode);
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extern BOOL dbgStrBtsEnable (BOOL enable);
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extern STATUS dbgStrPebsModeSet (INT32 event, INT32 metric, BOOL os,
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LL_INT * pValue);
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extern BOOL dbgStrPebsEnable (BOOL enable);
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extern void dbgStrShowInit (void);
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extern void dbgStrShow (WIND_TCB * pTcb, int type);
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#else /* __STDC__ */
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extern STATUS dbgStrLibInit ();
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extern DS_BUF_HEADER * dbgStrBufInit ();
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extern STATUS dbgStrBufAlloc ();
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extern STATUS dbgStrBufFree ();
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extern STATUS dbgStrConfig ();
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extern STATUS dbgStrStart ();
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extern STATUS dbgStrStop ();
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extern STATUS dbgStrBtsModeSet ();
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extern BOOL dbgStrBtsEnable ();
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extern STATUS dbgStrPebsModeSet ();
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extern BOOL dbgStrPebsEnable ();
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extern void dbgStrShowInit ();
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extern void dbgStrShow ();
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#endif /* __STDC__ */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCdbgStrLibh */
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