367 lines
15 KiB
C
367 lines
15 KiB
C
/* ppc604.h - PowerPC 604 specific header */
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/*
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* Copyright (c) 1996, 1998, 2001-2004, 2006-2007, 2010,
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* 2012 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01f,21nov12,ylu added load/store control register LDSTCR definition macro.
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(WIND00382987)
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02e,26mar12,cww Added dsisr bits 1 and 4
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02d,29apr10,swu fix PIR register write error. (WIND00208699)
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02c,22apr10,rgo CQID:209335 - PIR is not available for mv5100 w/ mpc750
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02b,19jul07,mmi add bit definitions and ICTC register for ppc745x, and _U
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versions of HID0 bit definitions
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02a,16jul07,pch CQ86377: re-enable MSR[FP] for syscall handler if enabled in
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caller
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01z,29jun07,pch CQ96747: add RI to _PPC_MSR_MMU_EXTRACT macro
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01y,12jan07,pch add HID0[TBEN] for MPC745x, and SVR for MPC8641
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01x,21nov06,pch MPC745x updates to MSSCR0 definitions
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01w,29sep06,lei added INT_UNMASK
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01v,01jun06,pch consolidate vector offset definitions in excPpcLib.h
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01u,08mar06,pch SPR 118651: add symbolic definitions for PVR values
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add snoop abstraction
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01t,01mar06,pch SPR 117925: add mention of SPRG4-7
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01s,26jul04,pch SPR 99846: Add support for _745x variant
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01r,16may04,mil Added _CPU_CACHE_ALIGN_SHIFT.
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01q,12feb04,jtp Add _WRS_MMU_CLASS_* macro
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01p,05dec03,jtp Add _WRS_TLB_MISS_CLASS_HW, _PPC_MSR_MMU_EXTRACT
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01o,13mar03,pch Add PPC32 support
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01n,12sep02,pch SPR 80642: add MSSCR0 for MPC7400 and MPC7410 L1 dCache flush
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01m,13jun02,jtp identify class of MMU support (SPR #78396)
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01l,23may02,pcs Implemented code review changes for Extra BAT support.
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01k,08may02,mil Relocated _EXC_OFF_PERF to avoid corruption by the extended
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_EXC_ALTIVEC_UNAVAILABLE vector (SPR #76916).
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Added _EXC_OFF_THERMAL for PPC604 (SPR #77552).
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01j,29apr02,pcs Add defined for EXTRA BAT support.
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01i,12dec01,kab add immr reg
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01h,02may01,dat 65984, Portable C Code, added HID1
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01g,30mar01,pcs ADDED _PPC_MSR_VEC if _WRS_ALTIVEC_SUPPORT is defined.
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01f,28mar01,dtr Adding define _WRS_ALTIVEC_SUPPORT.
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01e,09nov98,ms fixed last checkin - removed extra __cplusplus bracket.
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01d,14oct98,elg added hardware breakpoints for PPC603 and PPC604
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01c,08oct96,tam added MSR and HID0 bit definition macros.
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01b,09apr96,tpr added PowerPC 604 specific macros.
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01a,14feb96,tpr written.
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*/
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#ifndef __INCppc604h
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#define __INCppc604h
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* If compiling for a variant, the preprocessor symbol CPU_VARIANT will be
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* defined as the directory suffix, e.g. _745x for the MPC745x processors
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* (whose objects go in target/lib/ppc/PPC604/common_745x).
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*
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* We really want something like #if ("CPU_VARIANT" == "_745x")
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* which ANSI C does not allow. However, it does allow the expansion
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* of CPU_VARIANT to be re-expanded according to another #define.
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*/
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#ifdef CPU_VARIANT
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#define _745x 7450
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#if (CPU_VARIANT == _745x)
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#define PPC_745x 1
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#endif /* CPU_VARIANT == _745x */
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#undef _745x
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#endif /* CPU_VARIANT */
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#if (defined(PPC_745x))
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/*
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* Not including arch/ppc/sprg4_7.h here, because SPRG4-7 exist only in
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* 7445/7455 and later (PVR >= 0x8001xxxx) and PPC_745x also supports
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* the 7440, 7441, and 7450 (PVR = 0x8000xxxx). BSP's or kernel-mode
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* applications which do not need to support the earlier processors may
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* #include <arch/ppc/sprg4_7.h> to pick up the definitions of SPRG4-7.
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*/
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#endif /* PPC_745x */
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/* MMU supports TLB miss with hardware (not SRR0/SRR1) */
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#undef _WRS_TLB_MISS_CLASS_SW
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#define _WRS_TLB_MISS_CLASS_HW 1
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/* MMU uses SR registers to establish contexts */
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#undef _WRS_MMU_CLASS_PID_REG
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#define _WRS_MMU_CLASS_SR_REGS 1
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#undef _WRS_MMU_CLASS_NONE
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/*
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* MMU supports the M attribute bit, allowing the coherency-required property
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* to be configured on a per-page basis. Therefore, even when snooping is
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* enabled, cacheDmaMalloc needs to call arch support to set the M bit.
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*/
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#define _WRS_SNOOP_NEEDS_DMA_MALLOC_SUPPORT
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/*
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* This is essentially a compiler switch to remove/add altivec support
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* in the target src. The BSP code is controlled using INCLUDE_ALTIVEC
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* in config.h
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*/
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#define _WRS_ALTIVEC_SUPPORT 1
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/* Special Purpose Register PowerPC604 specific */
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#define IMMR 638 /* Internal mem map reg - from 82xx slave SIU */
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#undef ASR /* 64 bit implementation only */
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#define MMCR0 952 /* Monitor Mode Control Register 0 */
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#define PMC1 953 /* Performance Monitor Counter Register 1 */
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#define PMC2 954 /* Performance Monitor Counter Register 2 */
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#define SIA 955 /* Sampled Instruction Address Register */
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#define SDA 959 /* Sampled Data Address Register */
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#define HID0 1008 /* hardware implementation register 0 */
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#define HID1 1009 /* hardware implementation register 1 */
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#define HID2 1011 /* hardware implementation register 2 (MPC755)*/
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#define IABR 1010 /* Instruction Address Breakpoint Register */
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#define DABR 1013 /* Data Address Breakpoint Register */
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#define LDSTCR 1016 /* load/store control register */
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#ifdef PPC_745x
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#define PIR 1023 /* Processor Identification Register */
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#endif
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#ifdef PPC_745x
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#define _WRS_ARCH_HAS_DPM
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#define ICTC 1019 /* Instruction cache throttling */
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#endif
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#ifdef _WRS_ALTIVEC_SUPPORT
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/* MSSCR0 exists only in MPC74xx/8641 */
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#define MSSCR0 1014 /* Memory Subsystem Control Register */
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# ifdef PPC_745x
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/*
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* The following MSSCR0 fields exist in MPC744x, MPC745x, and MPC8641
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* (PVR=800xxxxx). We use the _PPC_MSSCR0_ID bit to recognize CPU 0
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* in the bootrom, and define the other fields here for completeness.
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*/
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#define _PPC_MSSCR0_DTQ_U 0x1c00 /* DTQ size */
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#define _PPC_MSSCR0_EIDIS_U 0x0100 /* disable external MPX intervention */
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#define _PPC_MSSCR0_L3TCEXT_U 0x0020 /* L3 turnaround clock count (7457) */
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#define _PPC_MSSCR0_ABD_U 0x0010 /* Address Bus Driven mode */
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#define _PPC_MSSCR0_L3TCEN_U 0x0008 /* L3 turnaround clock enable (7457) */
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#define _PPC_MSSCR0_L3TC_U 0x0006 /* L3 turnaround clock count (7457) */
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#define _PPC_MSSCR0_BMODE 0xc000 /* Bus Mode */
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#define _PPC_MSSCR0_ID 0x0020 /* Set if SMP CPU ID != 0 */
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#define _PPC_MSSCR0_BIT_ID 26
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#define _PPC_MSSCR0_L2PFE 0x0003 /* # of L2 prefetch engines enabled */
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# else /* PPC_745x */
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/*
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* The following MSSCR0 fields exist only in MPC7400 (PVR=000Cxxxx)
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* and MPC7410 (PVR=800Cxxxx). We use the DL1HWF bit in cacheALib.s,
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* and define the other fields here for completeness. All are in the
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* MS half of the register.
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*/
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#define _PPC_MSSCR0_SHDEN_U 0x8000 /* Shared-state (MESI) enable */
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#define _PPC_MSSCR0_SHDPEN3_U 0x4000 /* MEI mode SHD0/SHD1 signal enable */
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#define _PPC_MSSCR0_L1_INTVEN_U 0x3800 /* L1 data cache HIT intervention */
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#define _PPC_MSSCR0_L2_INTVEN_U 0x0700 /* L2 data cache HIT intervention */
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#define _PPC_MSSCR0_DL1HWF_U 0x0080 /* L1 data cache hardware flush */
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#define _PPC_MSSCR0_BIT_DL1HWF 8
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#define _PPC_MSSCR0_EMODE_U 0x0020 /* MPX bus mode (read-only) */
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#define _PPC_MSSCR0_ABD_U 0x0010 /* Address bus driven (read-only) */
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# endif /* PPC_745x */
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#endif /* _WRS_ALTIVEC_SUPPORT */
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#define _CPU_CACHE_ALIGN_SHIFT 5 /* cache line size = 32 */
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#undef _CPU_CACHE_ALIGN_SIZE
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#define _CPU_CACHE_ALIGN_SIZE 32 /* cannot use (1<<5) because compiler
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* directive __attribute__ cant hdl */
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/* spr976 - DMISS data tlb miss address register
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* spr977 - DCMP data tlb miss compare register
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* spr978 - HASH1 PTEG1 address register
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* spr980 - HASH2 PTEG2 address register
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* IMISS - instruction tlb miss address register
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* ICMP - instruction TLB mis compare register
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* RPA - real page address register
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* HID0 - hardware implemntation register
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* HID2 - instruction address breakpoint register
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*/
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#define _PPC_HID0_EMCP 0x80000000 /* Enable machine check pin */
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#define _PPC_HID0_ECPC 0x40000000 /* Enable cache parity check */
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#define _PPC_HID0_EBA 0x20000000 /* Enable address bus parity */
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#define _PPC_HID0_EBD 0x10000000 /* Enable data bus parity */
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# ifdef PPC_745x
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#define _PPC_HID0_TBEN 0x04000000 /* Enable timebase & decr */
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#define _PPC_HID0_NAP_U 0x0040 /* NAP power management mode */
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#define _PPC_HID0_SLEEP_U 0x0020 /* SLEEP power management mode */
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#define _PPC_HID0_DPM_U 0x0010 /* enable dynamic power management */
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#define _PPC_HID0_NAP 0x00400000 /* NAP power management mode */
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#define _PPC_HID0_SLEEP 0x00200000 /* SLEEP power management mode */
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#define _PPC_HID0_DPM 0x00100000 /* enable dynamic power management */
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# endif /* PPC_745x */
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#define _PPC_HID0_PAR 0x01000000
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#define _PPC_HID0_NHR 0x00010000 /* Not hard reset */
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#define _PPC_HID0_ICE 0x00008000 /* inst cache enable */
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#define _PPC_HID0_DCE 0x00004000 /* data cache enable */
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#define _PPC_HID0_ILOCK 0x00002000 /* inst cache lock */
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#define _PPC_HID0_DLOCK 0x00001000 /* data cache lock */
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#define _PPC_HID0_ICFI 0x00000800 /* inst cache flash invalidate*/
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#define _PPC_HID0_DCFI 0x00000400 /* data cache flash invalidate*/
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#define _PPC_HID0_SIED 0x00000080 /* serial instr exec disable */
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#define _PPC_HID0_DCFA 0x00000040 /* dCache flush assist on 7xx */
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#define _PPC_HID0_BHTE 0x00000004 /* branch history table enable*/
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#define _PPC_HID0_XBSEN 0x0100 /* Extended Block Size enable */
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# ifdef PPC_745x
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#define _PPC_HID0_TBEN_U 0x0400 /* Enable timebase & decr */
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#define _PPC_HID1_EMCP 0x80000000 /* Enable machine check pin */
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#define _PPC_HID1_EBA 0x20000000 /* Enable address bus parity */
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#define _PPC_HID1_EBD 0x10000000 /* Enable data bus parity */
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#define _PPC_HID1_DSF4 0x00400000 /* Dynamic frequency scaling */
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#define _PPC_HID1_DSF2 0x00200000 /* Dynamic frequency scaling */
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#define _PPC_HID1_PC5 0x00040000 /* PLL configuration bit 5 */
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#define _PPC_HID1_PC0 0x00020000 /* PLL configuration bit 0 */
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#define _PPC_HID1_PC1 0x00008000 /* PLL configuration bit 1 */
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#define _PPC_HID1_PC2 0x00004000 /* PLL configuration bit 2 */
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#define _PPC_HID1_PC3 0x00002000 /* PLL configuration bit 3 */
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#define _PPC_HID1_PC4 0x00001000 /* PLL configuration bit 4 */
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#define _PPC_HID1_SYNCBE 0x00000800 /* addr. broadcast for sync, eieio */
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#define _PPC_HID1_ABE 0x00000400 /* addr. broadcast enable */
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#define _PPC_ICTC_FI_MASK 0x000001FE /* Instruction forwarding interval */
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#define _PPC_ICTC_FI_45 0x0000005A /* fetch instr. every 45 cycles */
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#define _PPC_ICTC_FI_85 0x000000AA /* fetch instr. every 85 cycles */
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#define _PPC_ICTC_FI_130 0x00000104 /* fetch instr. every 130 cycles */
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#define _PPC_ICTC_FI_175 0x0000015E /* fetch instr. every 175 cycles */
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#define _PPC_ICTC_FI_210 0x000001A4 /* fetch instr. every 210 cycles */
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#define _PPC_ICTC_FI_255 0x000001FE /* fetch instr. every 255 cycles */
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#define _PPC_ICTC_FI_EN 0x00000001 /* Instruction cache throttling enable */
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# endif /* PPC_745x */
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#define _PPC_HID0_HIGH_BAT_EN_U 0x0080 /* High Bat enable on MPC7455 */
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#define _PPC_HID2_HIGH_BAT_EN_U 0x0004 /* High Bat enable on MPC755 */
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#define SVR 286 /* "system" version register */
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#define _PPC_SVR_VER_MASK 0xffffff00 /* "version" field */
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#define _PPC_SVR_REV_MASK 0x000000ff /* "revision" field */
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#define _PPC_SVR_MPC8641 0x80900000 /* single-core 8641 */
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#define _PPC_SVR_MPC8641D 0x80910000 /* dual-core 8641D */
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#define PVR 287 /* processor version register */
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/*
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* Values of upper half of PVR, used in cache code
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* to discern cache size and select flush algorithm
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*/
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#define _PPC_PVR_PPC604_U 0x0004
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#define _PPC_PVR_PPC750_U 0x0008
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#define _PPC_PVR_PPC604E_U 0x0009
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#define _PPC_PVR_PPC604R_U 0x000a
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#define _PPC_PVR_MPC7400_U 0x000c
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#define _PPC_PVR_MPC755_U 0x3200
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#define _PPC_PVR_MPC745_U 0x3202
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#define _PPC_PVR_PPC750FX_0_U 0x7000 /* lowest PPC750FX PVR value */
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#define _PPC_PVR_PPC750FX_f_U 0x700f /* highest PPC750FX PVR value */
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#define _PPC_PVR_MPC7450_U 0x8000 /* also 7440, 7441 */
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#define _PPC_PVR_MPC7455_U 0x8001 /* also 7445 */
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#define _PPC_PVR_MPC7457_U 0x8002 /* also 7447 */
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#define _PPC_PVR_MPC7447A_U 0x8003
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#define _PPC_PVR_MPC7448_U 0x8004
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#define _PPC_PVR_MPC7410_U 0x800c
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/* HID0 bit definitions */
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#define _PPC_HID0_BIT_ICE 16 /* HID0 ICE bit for 604 */
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#define _PPC_HID0_BIT_DCE 17 /* HID0 DCE bit for 604 */
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#define _PPC_HID0_BIT_ILOCK 18 /* HID0 ILOCK bit for 604 */
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#define _PPC_HID0_BIT_DLOCK 19 /* HID0 DLOCK bit for 604 */
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#define _PPC_HID0_BIT_ICFI 20 /* HID0 ICFI bit for 604 */
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#define _PPC_HID0_BIT_DCFI 21 /* HID0 DCFI bit for 604 */
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#define _PPC_HID0_BIT_SIED 24 /* HID0 SIED bit for 604 */
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#define _PPC_HID0_BIT_DCFA 25 /* HID0 DCFA bit for 7xx/74xx */
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#define _PPC_HID0_BIT_BHTE 29 /* HID0 BHTE bit for 604 */
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#define _PPC_HID0_BIT_XBSEN 23 /* HID0 XBSEN bit for 7455 */
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#define _PPC_HID0_BIT_HIGH_BAT_EN 8 /* HID0 HIGH_BAT_EN bit for 7455 */
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#define _PPC_HID2_BIT_HIGH_BAT_EN 13 /* HID2 HIGH_BAT_EN bit for 755 */
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/* MSR bit definitions */
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#define _PPC_MSR_BIT_POW 13 /* MSR Power Management bit - POW */
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#define _PPC_MSR_BIT_ILE 15 /* MSR Excep little endian bit - ILE */
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#define _PPC_MSR_BIT_FP 18 /* MSR Floating Ponit Aval. bit - FP */
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#define _PPC_MSR_BIT_FE0 20 /* MSR FP exception mode 0 bit - FE0 */
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#define _PPC_MSR_BIT_SE 21 /* MSR Single Step Trace bit - SE */
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#define _PPC_MSR_BIT_BE 22 /* MSR Branch Trace Enable bit - BE */
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#define _PPC_MSR_BIT_FE1 23 /* MSR FP exception mode 1 bit - FE1 */
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#define _PPC_MSR_BIT_IP 25 /* MSR Exception Prefix bit - EP */
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#define _PPC_MSR_BIT_IR 26 /* MSR Inst Translation bit - IR */
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#define _PPC_MSR_BIT_DR 27 /* MSR Data Translation bit - DR */
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#define _PPC_MSR_BIT_PM 29 /* MSR Performance Monitor bit - MR */
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#define _PPC_MSR_BIT_RI 30 /* MSR Exception Recoverable bit - RI */
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#ifdef _WRS_ALTIVEC_SUPPORT
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#define _PPC_MSR_VEC 0x0200 /* Bit 6 of MSR */
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#define _PPC_MSR_BIT_VEC 06 /* MSR Altivec Available bit - VEC */
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#endif /* _WRS_ALTIVEC_SUPPORT */
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/* MSR MMU/RI Bit extraction */
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#define _PPC_MSR_MMU_RI_EXTRACT(src, dst) \
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li dst, _PPC_MSR_IR | _PPC_MSR_DR | _PPC_MSR_RI ; \
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and dst, dst, src
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#define _PPC_MSR_MMU_RI_FP_EXTRACT(src, dst) \
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li dst, _PPC_MSR_IR | _PPC_MSR_DR | _PPC_MSR_RI | _PPC_MSR_FP ; \
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and dst, dst, src
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/* IABR bit definitions */
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/* set and get address in IABR */
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#define _PPC_IABR_ADD(x) ((x) & 0xFFFFFFFC)
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#define _PPC_IABR_BE 0x00000002 /* breakpoint enabled */
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#define _PPC_IABR_TE 0x00000001 /* translation enabled */
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/* DABR bits definition */
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/* set and get address in DABR */
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#define _PPC_DABR_DAB(x) ((x) & 0xFFFFFFF8)
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#define _PPC_DABR_BT 0x00000004 /* breakpoint translation */
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#define _PPC_DABR_DW 0x00000002 /* data write enable */
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#define _PPC_DABR_DR 0x00000001 /* data read enable */
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/* mask for read and write operations */
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#define _PPC_DABR_D_MSK (_PPC_DABR_DW | _PPC_DABR_DR)
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/* DSISR bits definition */
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#define _PPC_DSISR_TRANS 0x40000000 /* translation not found */
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#define _PPC_DSISR_ACCESS 0x08000000 /* access not permitted */
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#define _PPC_DSISR_BRK 0x00400000 /* DABR match occurs */
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/* set EE bit to 1 */
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#undef INT_UNMASK
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#define INT_UNMASK(reg) \
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mfmsr reg /* load msr */ ; \
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ori reg, reg, _PPC_MSR_EE /* set EE bit */ ; \
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mtmsr reg /* UNLOCK INTERRUPT */ ; \
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isync
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCppc604h */
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