231 lines
6.0 KiB
C
231 lines
6.0 KiB
C
/* mmuPpc800Lib.h - mmu library for PowerPc 800 series */
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/* Copyright 1984-2005 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01i,03feb05,mig Code review changes.
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01h,19jan05,mig Cleanup
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01g,05jan05,mig Fix protection states
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01f,22dec04,mig Fix protection states
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01e,24nov04,mig Support AIM MMU in VxWorks 6.0
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01d,29nov04,dtr Fix for AIM transition.
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01c,13nov03,jtp Support configAll.h change requiring MMU_PAGE_SIZE
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definition.
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01b,05feb97,tpr removed reserved macro (SPR 7783).
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01a,27apr96,tpr written.
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*/
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#ifndef __INCmmuPpc800Libh
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#define __INCmmuPpc800Libh
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Number of TLB Entry registers, expressed both as a power of two
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* as well as an integer.
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*/
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#define N_TLB_ENTRIES_BITS 6
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#define N_TLB_ENTRIES (1 << N_TLB_ENTRIES_BITS)
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#define MMU_I_ADDR_TRANS 0
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#define MMU_D_ADDR_TRANS 1
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#define MMU_INST 0x01
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#define MMU_DATA 0x02
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#define MMU_ASID_MIN 0
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#define MMU_ASID_MAX 15
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#define MMU_PAGE_SIZE_4K 0x00001000
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#define MMU_PAGE_SIZE_16K 0x00004000
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#define MMU_PAGE_SIZE_512K 0x00080000
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#define MMU_PAGE_SIZE_8M 0x00800000
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#define MMU_TLB_PAGE_SIZE_4K 0
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#define MMU_TLB_PAGE_SIZE_16K 0
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#define MMU_TLB_PAGE_SIZE_512K 1
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#define MMU_TLB_PAGE_SIZE_8M 3
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#define MMU_PAGE_SIZE MMU_PAGE_SIZE_4K
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#define MMU_PAGE_SIZE_8XX_MIN MMU_PAGE_SIZE
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#define MMU_STATE_VALID 0x00000001
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#define MMU_STATE_VALID_NOT 0x00000000
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#define MMU_STATE_WRITABLE 0x00000002
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#define MMU_STATE_WRITABLE_NOT 0x00000000
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#define MMU_STATE_CACHEABLE 0x00000000
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#define MMU_STATE_CACHEABLE_NOT 0x00000004
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#define MMU_STATE_CACHEABLE_WRITETHROUGH 0x00000008
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#define MMU_STATE_CACHEABLE_COPYBACK 0x00000000
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#define MMU_STATE_GUARDED 0x00000010
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#define MMU_STATE_GUARDED_NOT 0x00000000
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#define MMU_STATE_MASK_VALID 0x00000001
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#define MMU_STATE_MASK_WRITABLE 0x00000002
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#define MMU_STATE_MASK_CACHEABLE 0x0000000c
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#define MMU_STATE_MASK_GUARDED 0x00000010
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#define MMU_STATE_MASK_PROTECTION 0x00000700
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#define MMU_STATE_MASK_WRITEABLE_NOT 0x00000400
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#define MMU_RPN_SHIFT 0x0000000c
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#define MMU_PROT_SHIFT 0x00000008
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#define MMU_PP_MASK 0x00000003
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#define MMU_STATE_SUP_RWX 0x00000000
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#define MMU_STATE_SUP_RWX_USR_RX 0x00000100
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#define MMU_STATE_SUP_RWX_USR_RWX 0x00000200
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#define MMU_STATE_SUP_RX_USR_RX 0x00000300
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#define MMU_STATE_SUP_RX 0x00000400
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/*
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* Each context's MMU pages are mapped using a two-level page table
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* scheme. The level 1 table is called the REGION table and the level
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* 2 table is called a PAGE table.
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*
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* The most significant MMU_REGION_INDEX_BITS bits of the virtual
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* address are used as an index into the Region Table. Each entry is of
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* size 2 ^ MMU_REGION_ENTRY_BITS, typically a pointer to a PAGE table.
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*/
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#define MMU_REGION_INDEX_BITS 10 /* number of bits in index */
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#define MMU_REGION_TBL_ENTRIES (0x1 << MMU_REGION_INDEX_BITS)
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/* number of regions in table */
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#define MMU_REGION_ENTRY_BITS 2 /* size in bytes as pwr of 2 */
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#define MMU_REGION_INDEX_MASK 0xFFC00000
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#define MMU_REGION_INDEX_SHIFT 22
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/*
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* The next most significant MMU_PAGE_INDEX_BITS bits of the virtual
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* address are used as an index into the Page Table.
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*/
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#define MMU_PAGE_INDEX_BITS 10 /* number of bits in index */
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/* max number of page table entries */
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#define MMU_PAGE_TBL_ENTRIES (0x1 << MMU_PAGE_INDEX_BITS)
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#ifndef _ASMLANGUAGE
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/* Effective Address Definition */
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typedef union effectiveAddr /* effective Address structure */
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{
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struct
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{
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u_int l1index:10; /* Level 1 Index */
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u_int l2index:10; /* Level 2 Index */
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u_int po:12; /* Page Offset */
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} field;
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void * effAddr;
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} EFFECTIVE_ADDR;
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/* Real Address Definition */
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typedef union realAddress /* Real Address Structure */
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{
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struct /* Bit field description */
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{
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u_int rpn:20; /* Real Page Number */
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u_int po:12; /* Page Offset */
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}field;
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void * realAddr; /* Real Address */
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} REAL_ADDRESS;
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/* Level 1 Descriptor Definition */
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typedef union level_1_desc /* Level 1 descriptor format */
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{
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struct /* Bit field desciption */
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{
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u_int l2ba:20; /* Level 2 table Base Address */
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u_int reserved:3; /* Reserved */
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u_int apg:4; /* Access Protection Group */
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u_int g:1; /* Guarded storage attribute for entry */
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u_int ps:2; /* Page Size level one */
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u_int wt:1; /* Write Through attribute for entry */
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u_int v:1; /* Segment Valid bit */
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} field;
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u_int l1desc; /* Level 1 descriptor */
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} LEVEL_1_DESC;
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/* Level 1 Table pointer definition */
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typedef union level_1_tbl_ptr /* Level 1 Table pointer structure */
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{
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struct /* Bit field description */
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{
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u_int l1tb:20; /* Level 1 table Base */
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u_int l1index:10; /* Level 1 table Index */
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u_int reserved:2; /* Reserved */
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} field;
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LEVEL_1_DESC * pL1Desc; /* Level 1 descriptor table pointer */
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} LEVEL_1_TBL_PTR;
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/* Level 2 descriptor definition */
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typedef union level_2_desc /* Level 2 descriptor format */
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{
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struct /* Bit field desciption */
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{
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u_int rpn:20; /* Real Page Number */
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u_int pp:2; /* Page Protection */
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u_int ppe:1; /* Page Protection encoding */
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u_int c:1; /* Change bit */
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u_int spv:4; /* Sub Page Valid */
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u_int sps:1; /* Small Page Size */
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u_int sh:1; /* Shared Page */
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u_int ci:1; /* Cache Inhibit */
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u_int v:1; /* Page Valid bit */
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} field;
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u_int l2desc; /* Level 2 descriptor */
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} LEVEL_2_DESC;
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/* Level 2 Table pointer definition */
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typedef union level_2_tbl_ptr /* Level 2 Table pointer structure */
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{
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struct /* Bit field description */
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{
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u_int l2tb:20; /* Level 2 Table Base */
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u_int l2index:10; /* Level 2 table Index */
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u_int reserved:2; /* Reserved */
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} field;
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LEVEL_2_DESC * pL2Desc; /* Level 2 descriptor table pointer */
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} LEVEL_2_TBL_PTR;
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#define MMU8XX_PTE LEVEL_2_DESC
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#if defined(__STDC__) || defined(__cplusplus)
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extern STATUS mmu800LibInit (int mmuType);
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#else /* __STDC__ */
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extern STATUS mmu800LibInit ();
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#endif /* __STDC__ */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCmmuPpc800Libh */
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