230 lines
7.3 KiB
C
230 lines
7.3 KiB
C
/* mmuArmPalLib.h - ARM MPU library header file */
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/* Copyright (c) 2006, 2007, 2010, 2012 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement. No license to Wind River intellectual property rights
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* is granted herein. All rights not licensed by Wind River are reserved
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* by Wind River.
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*/
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/*
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modification history
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--------------------
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01e,16mar12,rec WIND00318272 - POSIX signals conformance
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01d,29apr10,pad Moved extern C statement after include statements.
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01c,21sep07,j_b add _func_mmuFaultAddrGet prototype
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01b,13jul06,m_h Generic MPU definitions
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01a,13jul06,m_h Created from mmuArmPalLib.h and vxWorks 5.5 mmuArmLib.h
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*/
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#ifndef __INCmpuArmPalLibh
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#define __INCmpuArmPalLibh
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#ifndef _ASMLANGUAGE
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#include <memLib.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#endif /* _ASMLANGUAGE */
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#define MPU_NUM_REGIONS 8
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#ifndef _ASMLANGUAGE
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#if (_BYTE_ORDER == _LITTLE_ENDIAN)
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typedef struct
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{
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UINT enable : 1; /* 1 => region enabled */
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UINT size : 5; /* size */
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UINT pad : 6; /* padding */
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UINT base : 20; /* region base address */
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} MPU_REGION_FIELDS;
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#else /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
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/* Big-Endian */
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typedef struct
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{
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UINT base : 20; /* region base address */
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UINT pad : 6; /* padding */
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UINT size : 5; /* size */
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UINT enable : 1; /* 1 => region enabled */
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} MPU_REGION_FIELDS;
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#endif /* (_BYTE_ORDER == _LITTLE_ENDIAN) */
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typedef union
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{
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MPU_REGION_FIELDS fields;
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UINT32 bits;
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} MPU_REGION_REG;
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typedef struct mpuTransTblStruct
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{
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MPU_REGION_REG regs[MPU_NUM_REGIONS];
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} MPU_TRANS_TBL;
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#endif /* _ASMLANGUAGE */
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/*
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* Architecture-dependent MPU states. These are states settable for regions.
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*/
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/* The size must be larger than 0x0A so zero in these fields
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* is an invalid MPU state is it is enabled (bit-0 = 1)
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*/
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#define MMU_STATE_INVALID_STATE 0xFFFFFFFF
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#define MPU_REGION_BASE_MASK 0xFFFFF000
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#define MPU_REGION_SIZE_MASK 0x0000003E
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#define MPU_REGION_SIZE_MAX 0x0000003E
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#define MMU_STATE_MASK_CACHEABLE 0xC0 /* CB bits */
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#define MMU_STATE_MASK_BUFFERABLE 0x40
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#define MMU_STATE_MASK_VALID 0x100 /* allows 4 AP bits */
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#define MMU_STATE_VALID 0x100 /* Full Access */
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#define MMU_STATE_VALID_NOT 0x000 /* No access */
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#ifdef MPU_USE_EXTENDED_PERMISSIONS
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#define MMU_STATE_NUM_AP_BITS 4
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#define MMU_STATE_MASK_PROTECTION 0xF
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#else /*MPU_USE_EXTENDED_PERMISSIONS*/
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#define MMU_STATE_NUM_AP_BITS 2
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#define MMU_STATE_MASK_PROTECTION 0x3
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#endif /*MPU_USE_EXTENDED_PERMISSIONS*/
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/* cacheable and bufferable states are not real physical bit definitions */
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#ifdef ARMCACHE_HAS_WRITETHROUGH
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/* Write-through mode is not available on all CPUs */
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#define MMU_STATE_CACHEABLE_WRITETHROUGH 0x80
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#endif /*ARMCACHE_HAS_WRITETHROUGH*/
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#define MMU_STATE_CACHE_BIT 0x80
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#define MMU_STATE_CACHEABLE_COPYBACK 0xC0
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/*
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* Set the default state to be copyback. CACHEABLE_WRITETHROUGH can also be
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* selected on 740T/946E.
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*/
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#define MMU_STATE_CACHEABLE MMU_STATE_CACHEABLE_COPYBACK
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#define MMU_STATE_CACHEABLE_NOT 0x0
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#define MMU_STATE_BUFFERABLE 0x40 /* bufferable, not cacheable */
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#define MMU_STATE_BUFFERABLE_NOT 0x0 /* will also set not cacheable*/
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/*
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* We need a size for a region that means the entire address
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* space. It is perfectly reasonable to wish to define such a region
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* and it is of course, not expressible within a UINT. So, define a
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* special size.
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*/
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#define MMU_ENTIRE_SPACE 0
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#define MMU_STATE_SUP_RW 0x01
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#define MMU_STATE_USR_RO_SUP_RW 0x02
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#define MMU_STATE_USR_RW_SUP_RW 0x03
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#define MMU_STATE_SUP_RO 0x05
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#define MMU_STATE_USR_RO_SUP_RO 0x06
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/*
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* When setting either of the attributes SPL_0 or SPL_1 it is necessary to:
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*
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* 1. specify MMU_ATTR_SPL_MSK ORred with MMU_ATTR_CACHE_MSK in the mask
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* argument to the routine, and:
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* 2. specify the appropriate cache state ORred in to the state argument
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* to the routine.
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*
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* So, to set a page as bufferable not cacheable, it is necessary to
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* specify both MMU_ATTR_SPL_0 and specify MMU_ATTR_CACHE_OFF in the
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* state argument. To mark a page as cacheable in the minicache,
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* MMU_ATTR_SPL_1 and MMU_ATTR_CACHE_COPYBACK must be specified in the
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* state argument. In both cases, specify MMU_ATTR_SPL_MSK ORred with
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* MMU_ATTR_CACHE_MSK in the mask argument.
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*
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* To "unset" the special attibutes SPL_0 or SPL_1, specify
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* MMU_ATTR_CACHE_MSK in the mask parameter (without MMU_ATTR_SPL_MSK),
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* and specify the cacheability required in the state argument.
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*
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* We provide the following alias on ARM, to make life easier.
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*/
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#define MMU_ATTR_BUFFERABLE (MMU_ATTR_SPL_0)
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/* MMU Control Register bit allocations */
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#define MMUCR_M_ENABLE (1<<0) /* MMU enable */
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#define MMUCR_A_ENABLE (1<<1) /* Address alignment fault enable */
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#define MMUCR_C_ENABLE (1<<2) /* (data) cache enable */
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#define MMUCR_W_ENABLE (1<<3) /* write buffer enable */
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#define MMUCR_PROG32 (1<<4) /* PROG32 */
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#define MMUCR_DATA32 (1<<5) /* DATA32 */
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#define MMUCR_L_ENABLE (1<<6) /* Late abort on earlier CPUs */
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#define MMUCR_BIGEND (1<<7) /* Big-endian (=1), little-endian (=0) */
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#define MMUCR_SYSTEM (1<<8) /* System bit, modifies MMU protections */
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#define MMUCR_ROM (1<<9) /* ROM bit, modifies MMU protections */
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#define MMUCR_F (1<<10) /* Should Be Zero */
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#define MMUCR_Z_ENABLE (1<<11) /* Branch prediction enable on 810 */
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#define MMUCR_I_ENABLE (1<<12) /* Instruction cache enable */
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#define MMUCR_V_ENABLE (1<<13) /* Exception vectors remap to 0xFFFF0000 */
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#define MMUCR_ALTVECT MMUCR_V_ENABLE /* alternate vector select */
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#define MMUCR_RR_ENABLE (1<<14) /* Round robin cache replacement enable */
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#define MMUCR_ROUND_ROBIN MMUCR_RR_ENABLE /* round-robin placement */
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#define MMUCR_DISABLE_TBIT (1<<15) /* disable TBIT */
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#define MMUCR_DSRAM_EN (1<<16) /* D-SRAM enable */
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#define MMUCR_DSRAM_LOADMODE (1<<17) /* D-SRAM load mode select */
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#define MMUCR_ISRAM_EN (1<<18) /* I-SRAM enable */
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#define MMUCR_ISRAM_LOADMODE (1<<19) /* I-SRAM load mode select */
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#ifndef _ASMLANGUAGE
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/* Externally visible mpuLib routines */
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IMPORT UINT32 mmuReadId (void);
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IMPORT UINT32 (* mmuCrGet) (void);
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IMPORT void (* mmuModifyCr) (UINT32 value, UINT32 mask);
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IMPORT UINT32 mmuHardCrGet (void);
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IMPORT UINT32 mmuSoftCrGet (void);
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IMPORT void mmuModifyHardCr (UINT32 value, UINT32 mask);
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IMPORT void mmuModifySoftCr (UINT32 value, UINT32 mask);
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IMPORT UINT32 (* _func_mmuFaultAddrGet) (void);
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IMPORT UINT32 (* _func_mmuFaultStatusGet) (void);
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#if (CPU == ARMARCH6) || (CPU==ARMARCH7) || (CPU==ARMARCH7_T2)
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IMPORT UINT32 (* _func_mmuIFaultStatusGet) (void);
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#endif /* ARMARCH6 || ARMARCH7 || ARMARCH7_T2 */
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IMPORT void mpuPrrSet (const MPU_REGION_REG *pRegs);
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IMPORT void mpuPrrGet (MPU_REGION_REG *pRegs);
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IMPORT void mpuCcrSet (UINT32 val);
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IMPORT UINT32 mpuCcrGet (void);
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IMPORT void mpuWbcrSet (UINT32 val);
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IMPORT UINT32 mpuWbcrGet (void);
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IMPORT void mpuPrSet (UINT32 val);
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IMPORT UINT32 mpuPrGet (void);
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IMPORT void mpuAEnable (UINT32 cacheState);
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IMPORT void mpuADisable (void);
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IMPORT UINT32 mpuGetEnable (void);
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCmpuArmPalLibh */
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