79 lines
1.8 KiB
C
79 lines
1.8 KiB
C
/* cacheArmManzanoLib.h - ARM XScale cache library header file */
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/* Copyright 199-2005 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01i,22feb06,m_h Manzano Support
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01h,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
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01g,07dec04,jb Further Palify ARM Aim cache
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01f,01dec03,scm flushing out aim...
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01e,25jul01,scm add btbInvalidate...
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01d,23jul01,scm change XScale name to conform to coding standards...
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01c,09feb01,scm add support for cache & TLB locking...
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01b,19dec00,scm correct cache sizes...
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01a,31aug00,scm created
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*/
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#ifndef __INCcacheArmManzanoLibh
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#define __INCcacheArmManzanoLibh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define D_CACHE_SIZE (32*1024) /* 32 kbytes DCache */
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#define I_CACHE_SIZE (32*1024) /* 32 kbytes ICache */
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#define MINI_CACHE_SIZE (2*1024) /* 2 kbytes minicache */
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#define MINI_CACHE_LINE_SIZE 32 /* 32 bytes per line*/
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/*
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* Some cache designs (e.g. Harvard) have D-cache either fully or
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* partially not coherent with I-cache
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*/
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#define ARMCACHE_NOT_COHERENT TRUE
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/*
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* This is a writethrough cache
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*/
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#define ARMCACHE_HAS_WRITETHROUGH TRUE
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/*
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* Has a mini-cache
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*/
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#define ARMCACHE_HAS_MINICACHE TRUE
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/*
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* Does not need an Instruction Memory Barrier
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*/
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#define ARMCACHE_NEEDS_IMB FALSE
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#ifndef _ASMLANGUAGE
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IMPORT void cacheArmManzanoLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
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PHYS_ADDR(virtToPhys) (VIRT_ADDR));
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/* definitions to allow for non-cacheAim direct calls */
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#define cacheArmManzanoDClearDisable cacheAimManzanoDClearDisable
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#define cacheArmManzanoIClearDisable cacheAimManzanoIClearDisable
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IMPORT void cacheAimManzanoDClearDisable (void);
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IMPORT void cacheAimManzanoIClearDisable (void);
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCcacheArmManzanoLibh */
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