422 lines
15 KiB
C
422 lines
15 KiB
C
/* smpI86P.h - i80x86 private SMP assembler definitions header file */
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/*
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* Copyright (c) 2006-2013, 2018 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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02n,18jul18,r_h Add kernel page table isolation support (F10571)
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02m,16may13,scm WIND00417700 SMP diab macro correction...
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02l,09jan13,scm WIND00229494 - SMP dedicated segment register
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02k,20dec12,yjw clear warning when load symbol table.(WIND00380360)
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02j,11sep12,cwl Correct the macro _WRS_WIND_VARS_ARCH_GET for UP.
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(WIND00375599)
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02i,27jan12,scm WIND00326315 - live lock osm & cpc issue...
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02h,10aug11,zl added _WRS_CPU_SMTSET_GET()
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02g,04jan11,scm WIND00248698 adjust vxIntStackEnabled to type BOOL...
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02f,12nov10,pch CQ240922: exclude refs to OSM when small footprint selected
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02e,25oct10,rbc WIND00204240 - Add support for objVerifiedSafe.
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02d,29jul10,pad Moved extern C statement after include statements.
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02c,24may10,jb Mods for SMP M-N support
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02b,05may10,jl add support for SMP GuestOS
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02a,07may09,pee using generated offsets. Removing hardcoded offsets.
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01z,15may09,gls moved VX_INSTR_BARRIER() to vxAtomicArchLibCommon.h
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01y,12feb09,sem Added sysCr3 to the WIND_VARS_ARCH struct
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Added sysCr3 access macros
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01x,18sep08,gls added _WRS_KERNEL_LOCK_VAR_ALIGN
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01w,27aug08,jpb Renamed VSB header file
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01v,30jul08,rbc Fix undefines for _IA32_LOC_APIC_ID...
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01u,24jun08,jpb Added include path for kernel configurations options set in
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vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
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01t,20jun08,zl replaced _WRS_ASM() with _WRS_BARRIER()
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01s,22apr08,zl ensure 32-bit _IA32_LOC_APIC_ID register access.
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01r,10jan08,gls added VX_INSTR_BARRIER()
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01q,01aug07,scm optimize _WRS_CPU_INDEX_GET()...
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01p,31may07,scm add _IA32_CPU_ADRS_BASE_GET macro...
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01o,04may07,scm correct _IA32_PER_CPU_VALUE_SET macro...
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01m,17apr07,kk move VX_MAX_SMP_CPUS to archI86.h
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01l,11dec06,kk removed references to VX_KERNEL_VARS define, no longer needed
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01k,06dec06,scm correct macro for GNU compiler support...
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01j,28nov06,scm remove def for _WRS_WIND_VARS_OFFSET_archVars...
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01i,02nov06,scm rename pSysGdtCurrent for backward comp with P2/3/4...
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01h,26oct06,scm add per Cpu OSM Scratch memory space for GDT data manipulation
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01g,05oct06,scm add translation to _IA32_CPU_INDEX_GET...
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01f,03oct06,scm additional macro work...
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01e,15sep06,scm add specific vxKernelVars[] support...
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01d,30aug06,scm expand _WRS_WIND_VARS_ARCH...
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01c,21aug06,jb Combining smpI86P.h and vxCpuLibP.h
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01b,01aug06,scm more SMP work...
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01a,21jul06,scm created, added SMP Support Macros...
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*/
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#ifndef __INCasmI86Ph
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#define __INCasmI86Ph
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/************************************************************/
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#include <vsbConfig.h>
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#include <arch/i86/archI86.h>
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#include <arch/i86/regsI86.h>
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#include <private/kernelLockLibP.h>
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#include <hwif/cpu/arch/i86/vxCpuIdLib.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define _WRS_ARCH_SUPPORTS_VX_CPU_STATE_INIT
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/*
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* 0xFEE00020 is the address of the local APIC ID Register.
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*/
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#define _IA32_LOC_APIC_ID 0xFEE00020
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#define _IA32_CPU_INDEX_SHIFT (0x18)
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#define _IA32_CPU_INDEX_MASK (0xFF)
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#ifdef _WRS_CONFIG_SMP
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/*
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* IA32 has been adapted to use the new object safe count feature for SMP.
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* When all architectures have been adapted this can be removed from
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* the code.
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*/
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#define _WRS_ARCH_HAS_OBJ_SAFE
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/*
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* This macro defines the alignment requirement for the WIND_VARS structure.
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*
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* There are 3 factors involved in selection of this value.
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*
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* 1. It's definition is no LESS than the maximum value of
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* _CPU_CACHE_ALIGN_SIZE, and may be larger to provide for future
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* cache line length growth.
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* 2. It must be at least as large as the WIND_VARS structure.
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* 3. It must be a power of 2.
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*
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* For example:
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* If WIND_VARS is 56 bytes, _WRS_WIND_VARS_ALIGN must be no less than 64
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* (rule 1).
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* If WIND_VARS is 72 bytes, _WRS_WIND_VARS_ALIGN must be no less than 128
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* (rules 2 and 3).
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*
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* For KPTI the alignment has to match WIND_RTP_VARS_ARCH; for that, we need
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* _WRS_WIND_RTP_VARS_ALIGN bytes.
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*/
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#ifdef _WRS_CONFIG_KPTI
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#define _WRS_WIND_VARS_ALIGN _WRS_WIND_RTP_VARS_ALIGN
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#define _WRS_WIND_VARS_ALIGN_SHIFT _WRS_WIND_RTP_VARS_ALIGN_SHIFT
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#else
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#define _WRS_WIND_VARS_ALIGN 128
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#define _WRS_WIND_VARS_ALIGN_SHIFT 7
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#endif
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/*
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* Much like the _WRS_WIND_VARS_ALIGN the _WRS_KERNEL_LOCK_VAR_ALIGN macro
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* must be defined for the common CPU build variants (e.g. PPC32, MIPS32,
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* XSCALE, etc), representing the maximum cache line size of the variants of
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* the respective arch.
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*
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* For x86 this is 128 bytes.
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*/
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#define _WRS_KERNEL_LOCK_VAR_ALIGN 128
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#ifndef _ASMLANGUAGE
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#ifdef _WRS_CONFIG_WRHV_GUEST
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/*
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* wrhvVbCpuId is used to store the address of the virtual-core's cpuId.
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* This global contains the virtual address for the core configuration
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* and avoids making a VBI function call to get the wrhvVbConfig address
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* and calculate the offset to the core id..
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*/
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extern UINT32 *wrhvVbCpuId;
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#endif /* WRS_CONFIG_WRHV_GUEST */
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/* mpCpuIndexTable is used in vxCpuArchLib.c, this gloabal avoids
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* calling through vxbus and reduces overhead, table translations
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* are done everywhere, but once up this table should never change...
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*/
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extern UINT8 mpCpuIndexTable[];
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typedef struct wind_vars_arch
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{
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GDT *cpu_pSysGdt; /* 0x4c: Global Descriptor Table */
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TSS *cpu_sysTssCurrent; /* 0x50: Task State Segmnet */
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TSS *cpu_excOSMTssCurrent; /* 0x54: OSM TSS */
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SEGDESC *cpu_sysOSMLdtCurrent; /* 0x58: Local Descriptor Table */
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UINT32 *cpu_excOSMStackCurrent; /* 0x5c: OSM Stack */
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UINT32 *cpu_sysOSMGdtScratchCurrent; /* 0x60: OSM Scratch memory */
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UINT32 cpu_vxIntStackPtr; /* 0x64: Interrupt Stack Pointer */
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BOOL cpu_vxIntStackEnabled; /* 0x68: Interrupt Stack Enabled */
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unsigned int cpu_cpuIndex; /* 0x6c: logical cpu used by GS */
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UINT32 cpu_cpuGsBaseCurrent; /* 0x70: &vxKernelVars in gsbase */
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UINT32 cpu_intNest; /* 0x74: Interrupt Nested Count */
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UINT32 cpu_sysCr3; /* 0x78: Local CR3 cache */
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UINT32 cpu_sysOSMState; /* 0x7c: OSM State Flag */
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} WIND_VARS_ARCH;
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#define _WRS_WIND_VARS_ARCH WIND_VARS_ARCH cpu_archVars
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/* macro to access the arch-specific fields of the vxKernelVars struct */
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#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
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_WRS_KERNEL_GLOBAL_ACCESS (archVars.cpu_##glob)
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#define _WRS_WIND_VARS_ARCH_SET(cpuid,glob,var) \
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_WRS_KERNEL_CPU_GLOBAL_SET(cpuid,archVars.cpu_##glob,var)
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#define _WRS_WIND_VARS_ARCH_GET(cpuid,glob) \
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_WRS_KERNEL_CPU_GLOBAL_GET(cpuid,archVars.cpu_##glob)
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#define _WRS_ARCH_LOCKED_GLOBAL_SET(glob, var) \
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_WRS_KERNEL_LOCKED_GLOBAL_SET(archVars.cpu_##glob,var)
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#define _WRS_ARCH_LOCKED_GLOBAL_GET(glob, var) \
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_WRS_KERNEL_LOCKED_GLOBAL_GET(archVars.cpu_##glob,var)
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/*
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* _WRS_CPU_SMTSET_GET() is used by the SMP scheduler for Hyper-Threading
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* support.
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*/
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#define _WRS_CPU_SMTSET_GET(smtSet, cpuIx) \
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smtSet = sysCpuIdTopology.__smtSet[cpuIx]
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/* Fast retrieve of cpuIndex using GS Base register offset */
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#if defined (__DCC__)
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__asm volatile unsigned int _vxGsBaseCpuIndexGet_inline (void)
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{
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! "ax" /* ax is clobbered */
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mov %gs:(0x6c), %eax
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}
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#else /* if defined (__GNUC__) */
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static __inline__ unsigned int _vxGsBaseCpuIndexGet_inline (void)
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{
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unsigned int cpu;
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__asm__ volatile ("mov %%gs:(0x6c), %%eax" \
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: "=a" (cpu) : /* no input */);
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return cpu;
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}
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#endif /* __DCC__ */
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#endif /* !_ASMLANGUAGE */
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#ifdef _WRS_CONFIG_WRHV_GUEST
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#define _WRS_CPU_INDEX_GET() \
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(*(volatile UINT32 *)wrhvVbCpuId)
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#else /* _WRS_CONFIG_WRHV_GUEST */
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#define _WRS_CPU_INDEX_GET() _vxGsBaseCpuIndexGet_inline ()
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#endif /* _WRS_CONFIG_WRHV_GUEST */
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#else /* _WRS_CONFIG_SMP */
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#define _WRS_CPU_INDEX_GET() 0
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/* macro to access the arch-specific fields */
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#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
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_WRS_KERNEL_GLOBAL_ACCESS (glob)
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#define _WRS_WIND_VARS_ARCH_SET(ignored,glob,var) \
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_WRS_KERNEL_CPU_GLOBAL_SET(ignored,glob,var)
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#define _WRS_WIND_VARS_ARCH_GET(ignored,glob) \
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_WRS_KERNEL_CPU_GLOBAL_GET(ignored,glob)
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#define _WRS_ARCH_LOCKED_GLOBAL_SET(glob, var) \
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_WRS_KERNEL_LOCKED_GLOBAL_SET(glob,var)
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#define _WRS_ARCH_LOCKED_GLOBAL_GET(glob, var) \
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_WRS_KERNEL_LOCKED_GLOBAL_GET(glob,var)
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#endif /* _WRS_CONFIG_SMP */
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#ifdef _ASMLANGUAGE
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#include <private/windLibP.h>
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#if defined(_WRS_CONFIG_SMP)
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/* generated macro values required by assembly macros below */
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#include <private/offsetMacrosP.h>
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/* SMP support */
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#define _WRS_LOAD_REG_WITH_VAR_BASE(label,reg) \
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leal FUNC(vxKernelVars),reg; \
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addl $_WIND_VARS_cpu_##label##_OFFSET,reg;
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#define _WRS_WIND_VARS_OFFSET(reg) \
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rol $_WRS_WIND_VARS_ALIGN_SHIFT,reg;
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#define _IA32_ASM_EXTERN_KERNEL_GLOBALS
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#ifdef _WRS_CONFIG_WRHV_GUEST
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#define _IA32_CPU_INDEX_GET(reg,scratch) \
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movl wrhvVbCpuId,reg; \
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movl 0x0(reg),reg;
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#else /* _WRS_CONFIG_WRHV_GUEST */
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#define _IA32_CPU_INDEX_GET(reg,scratch) \
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movl $_IA32_LOC_APIC_ID,reg; \
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movl 0x0(reg),reg; \
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ror $_IA32_CPU_INDEX_SHIFT,reg; \
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andl $_IA32_CPU_INDEX_MASK,reg; \
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leal FUNC(mpCpuIndexTable)(reg),scratch; \
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mov 0x0(scratch),reg; \
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andl $_IA32_CPU_INDEX_MASK,reg; \
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subl FUNC(vxBaseCpuPhysIndex), reg;
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#endif /* _WRS_CONFIG_WRHV_GUEST */
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/*
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* Obtain the address of vxKernelVars[cpuid] for the current
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* CPU in register 'reg', using 'scratch' as a scratch
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* variable.
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*/
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#define _IA32_CPU_ADRS_BASE_GET(reg,scratch) \
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_IA32_CPU_INDEX_GET(reg,scratch) \
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_WRS_WIND_VARS_OFFSET(reg) \
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leal FUNC(vxKernelVars)(reg), reg;
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#define _IA32_PER_CPU_ADRS_GET(reg,scratch,label) \
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_IA32_CPU_INDEX_GET(reg,scratch) \
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_WRS_WIND_VARS_OFFSET(reg) \
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
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addl reg,scratch; \
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leal 0x0(scratch),reg;
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#define _IA32_PER_CPU_VALUE_GET(reg,scratch,label) \
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_IA32_CPU_INDEX_GET(reg,scratch) \
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_WRS_WIND_VARS_OFFSET(reg) \
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
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addl reg,scratch; \
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movl 0x0(scratch),reg;
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#define _IA32_PER_CPU_VALUE_SET(regv,scr1,scr2,label) \
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_IA32_CPU_INDEX_GET(scr1,scr2) \
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_WRS_WIND_VARS_OFFSET(scr1) \
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scr2) \
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addl scr1,scr2; \
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movl regv,0x0(scr2);
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#define _IA32_PER_CPU_VALUE_AND_ADRS_GET(regv,rega,scratch,label) \
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_IA32_CPU_INDEX_GET(regv,scratch) \
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_WRS_WIND_VARS_OFFSET(regv) \
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
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addl regv,scratch; \
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leal 0x0(scratch),rega; \
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movl 0x0(scratch),regv;
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#define _IA32_PER_CPU_VALUE_INC(reg,scratch,label) \
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_IA32_CPU_INDEX_GET(reg,scratch) \
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_WRS_WIND_VARS_OFFSET(reg) \
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
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addl reg,scratch; \
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movl 0x0(scratch),reg; \
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incl reg; \
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movl reg,0x0(scratch);
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#define _IA32_PER_CPU_VALUE_DEC(reg,scratch,label) \
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_IA32_CPU_INDEX_GET(reg,scratch) \
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_WRS_WIND_VARS_OFFSET(reg) \
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
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addl reg,scratch; \
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movl 0x0(scratch),reg; \
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decl reg; \
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movl reg,0x0(scratch);
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/*
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* rega = register to store kernel lock owner
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* regb = register to store cpu index
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*
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* typedef struct smpLock
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* {
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* volatile int state; /@ state of lock (free/taken) @/
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* volatile int owner; /@ CPU which owns the lock @/
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* int count; /@ recursive ownership nesting count @/
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* int options; /@ options applicable to this lock @/
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*/
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#define _IA32_KERNEL_LOCK_OWNER_AND_INDEX_GET(rega, regb) \
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_IA32_CPU_INDEX_GET(regb,rega) \
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leal FUNC(kernelStateLock),rega; \
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movl VX_KERNEL_LOCK_cpuIndex_OFFSET(rega),rega;
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/* kernel spin lock owner */
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#else /* _WRS_CONFIG_SMP */
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#define _WRS_IA32_VAR_ADRS(label) FUNC(label)
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#ifdef _WRS_CONFIG_MEM_ALLOT
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/* exclude OSM references, because OSM requires malloc() */
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#define _IA32_ASM_EXTERN_KERNEL_GLOBALS \
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.globl FUNC(pSysGdt); /* Gdt */ \
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.globl FUNC(intNest); /* nested intr cnt */ \
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.globl FUNC(vxIntStackPtr); /* intr stk ptr */ \
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.globl FUNC(vxIntStackEnabled); /* intr stk enabled flag */ \
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.globl FUNC(sysCr3); /* local CR3 cache */
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#else /* _WRS_CONFIG_MEM_ALLOT */
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#define _IA32_ASM_EXTERN_KERNEL_GLOBALS \
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.globl FUNC(sysTssCurrent); /* OSM Tss task info */ \
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.globl FUNC(excOSMTssCurrent); /* OSM Tss */ \
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.globl FUNC(sysOSMGdtScratchCurrent); /* OSM Scratch memory */ \
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.globl FUNC(sysOSMState); /* OSM State Flag */ \
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.globl FUNC(pSysGdt); /* Gdt */ \
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.globl FUNC(intNest); /* nested intr cnt */ \
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.globl FUNC(vxIntStackPtr); /* intr stk ptr */ \
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.globl FUNC(vxIntStackEnabled); /* intr stk enabled flag */ \
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.globl FUNC(sysCr3); /* local CR3 cache */
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#endif /* _WRS_CONFIG_MEM_ALLOT */
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#define _IA32_PER_CPU_ADRS_GET(reg,scratch,label) \
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leal _WRS_IA32_VAR_ADRS(label),reg; /* get address of label */
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#define _IA32_PER_CPU_VALUE_GET(reg,scratch,label) \
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movl _WRS_IA32_VAR_ADRS(label),reg; /* get value at label */
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#define _IA32_PER_CPU_VALUE_SET(regv,scr1,scr2,label) \
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movl regv,_WRS_IA32_VAR_ADRS(label);
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#define _IA32_PER_CPU_VALUE_AND_ADRS_GET(regv,rega,label) \
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leal _WRS_IA32_VAR_ADRS(label),rega; /* get address of label */ \
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leal 0x0(rega),regv; /* get value at label */
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#define _IA32_PER_CPU_VALUE_INC(reg,scratch,label) \
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incl _WRS_IA32_VAR_ADRS(label);
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#define _IA32_PER_CPU_VALUE_DEC(reg,scratch,label) \
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decl _WRS_IA32_VAR_ADRS(label);
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#endif /* _ASMLANGUAGE */
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#endif /* _WRS_CONFIG_SMP */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCasmI86Ph */
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