191 lines
6.2 KiB
C
191 lines
6.2 KiB
C
/* smcFdc37b78x.h - a super i/o initialization include module */
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/* Copyright 1984-1993 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01a,28mar00,mks written.
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*/
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/*
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DESCRIPTION
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This file contains mnemonics for SUPER I/0 (fdc37b78x) chip initialization.
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*/
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#ifndef INCsmcfdc37b78xh
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#define INCsmcfdc37b78xh
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/* defines */
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/* wiring-dependent SMCFDC37B78X variables */
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#ifndef SMCFDC37B78X_CONFIG_PORT
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#define SMCFDC37B78X_CONFIG_PORT 0x0370
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#endif
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#ifndef SMCFDC37B78X_INDEX_PORT
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#define SMCFDC37B78X_INDEX_PORT 0x0370
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#endif
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#ifndef SMCFDC37B78X_DATA_PORT
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#define SMCFDC37B78X_DATA_PORT (SMCFDC37B78X_INDEX_PORT + 1)
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#endif
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#define SMCFDC37B78XWRT(ioPort, value) sysOutByte (ioPort, value)
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#define SMCFDC37B78XRD(ioPort) sysInByte (ioPort)
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/* configuration mode begin command */
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#define SMCFDC37B78X_CONFIG_START 0x55
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/* configuration mode end command */
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#define SMCFDC37B78X_CONFIG_END 0xAA
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/* chip level registers */
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/* logical device configuration register */
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#define SMCFDC37B7X_LOGDEVCFGREG 0x07
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/* logical device level registers */
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#define SMCFDC37B78X_LOGDEV_ACTIVATE 0x30 /* activation register */
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#define SMCFDC37B78X_IOBASE_HIGH 0x60 /* i/o base - high byte */
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#define SMCFDC37B78X_IOBASE_LOW 0x61 /* i/o base - low byte */
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#define SMCFDC37B78X_INTERRUPT 0x70 /* interrupt config */
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#define SMCFDC37B78X_MODE 0xF0 /* mode register */
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/* defined logical devices */
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#define SMCFDC37B78X_FDD 0x00 /* floppy disk drive */
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#define SMCFDC37B78X_LPT1 0x03 /* parallel port */
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#define SMCFDC37B78X_COM1 0x04 /* serial device - port 1 */
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#define SMCFDC37B78X_COM2 0x05 /* serial device - port 2 */
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#define SMCFDC37B78X_KBD 0x07 /* keyboard */
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#define SMCFDC37B78X_AUX 0x08 /* auxiliary i/o */
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#define SMCFDC37B78X_ACPI 0x0A /* ACPI */
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/* use these defines for enabling specific device. DON'T USE ONE ABOVE. */
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#define SMCFDC37B78X_FDD_EN 0x01 /* floppy disk drive */
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#define SMCFDC37B78X_LPT1_EN 0x02 /* parallel port */
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#define SMCFDC37B78X_COM1_EN 0x04 /* serial device - port 1 */
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#define SMCFDC37B78X_COM2_EN 0x08 /* serial device - port 2 */
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#define SMCFDC37B78X_KBD_EN 0x10 /* keyboard */
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/* device specific intialization values */
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#define SMCFDC37B78X_ACT_DEV 0x01 /* activate device */
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#define SMCFDC37B78X_COM_HSM 0x02 /* enable high speed services on COM */
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#define SMCFDC37B78X_INTR_KBD 0x01 /* irq line # 1 tied to KBD */
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#define SMCFDC37B78X_INTR_COM1 0x04 /* irq line # 4 tied to COM 1 */
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#define SMCFDC37B78X_INTR_COM2 0x03 /* irq line # 5 tied to COM 2 */
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#define SMCFDC37B78X_INTR_LPT1 0x07 /* irq line # 7 tied to LPT */
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#define SMCFDC37B78X_COM_MCR 0x04
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#define SMCFDC37B78X_COM_MCROUT2 0x08
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#define SMCFDC37B78X_COM_MCROUT2_MASK 0x08
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#define SMCFDC37B78X_COM1_IOHIGH 0x03 /* COM1, i/o high byte */
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#define SMCFDC37B78X_COM1_IOLOW 0xF8 /* COM1, i/o low byte */
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#define SMCFDC37B78X_COM1_IOBASE 0x03F8 /* COM1, i/o address */
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#define SMCFDC37B78X_COM1_MCR (SMCFDC37B78X_COM1_IOBASE + \
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SMCFDC37B78X_COM_MCR)
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#define SMCFDC37B78X_COM2_IOHIGH 0x02 /* COM2, i/o high byte */
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#define SMCFDC37B78X_COM2_IOLOW 0xF8 /* COM2, i/o low byte */
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#define SMCFDC37B78X_COM2_IOBASE 0x02F8 /* COM2, i/o address */
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#define SMCFDC37B78X_COM2_MCR (SMCFDC37B78X_COM2_IOBASE + \
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SMCFDC37B78X_COM_MCR)
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#define SMCFDC37B78X_LPT1_IOHIGH 0x03 /* LPT1, i/o high byte */
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#define SMCFDC37B78X_LPT1_IOLOW 0xBC /* LPT1, i/o low byte */
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#define SMCFDC37B78X_LPT1_IOBASE 0x03BC /* LPT1, i/o address */
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/* GPIO Stuff */
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#define SMCFDC37B78X_IRQMUX_IDX 0xC0 /* IRQ Mux register */
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#define SMCFDC37B78X_IRQ_PARALLEL 0x07
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#define SMCFDC37B78X_GP53_INDEX 0xD4 /* IRQ 2 pin */
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#define SMCFDC37B78X_GP53_IRQ11_OUT 0x08
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#define SMCFDC37B78X_GP60_INDEX 0xD0 /* IRQ 1 pin */
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#define SMCFDC37B78X_GP60_IRQ1_OUT 0x08
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#define SMCFDC37B78X_GP61_INDEX 0xD1 /* IRQ 3 pin */
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#define SMCFDC37B78X_GP61_IRQ3_OUT 0x08
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#define SMCFDC37B78X_GP62_INDEX 0xD2 /* IRQ 4 pin */
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#define SMCFDC37B78X_GP62_IRQ4_OUT 0x08
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#define SMCFDC37B78X_GP64_INDEX 0xD4 /* IRQ 6 pin */
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#define SMCFDC37B78X_GP64_IRQ6_OUT 0x08
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#define SMCFDC37B78X_GP65_INDEX 0xD5 /* IRQ 7 pin */
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#define SMCFDC37B78X_GP65_IRQ7_OUT 0x08
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/* defined masks */
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#define SMCFDC37B78X_COM_HSM_MASK 0x00
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#define SMCFDC37B78X_GP_FUNC_MASK 0xBB
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#define SMCFDC37B78X_IRQ_PARALLEL_MASK 0x07
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#define SMCFDC37B78X_MASK_ALL 0xFF
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/* keyboard specific defines */
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#define SMCFDC37B78X_KBD_DATA 0x60 /* ISA port addresses */
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#define SMCFDC37B78X_KBD_CTLSTS 0x64
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#define SMCFDC37B78X_KBD_CCMD_SELFTEST 0xAA /* kbd controller commands */
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#define SMCFDC37B78X_KBD_CCMD_IFCTEST 0xAB
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#define SMCFDC37B78X_KBD_CCMD_WRTPORT2 0xD1
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#define SMCFDC37B78X_KBD_CTLSTS_IBF 0x2 /* kbd status bit [1:0] */
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#define SMCFDC37B78X_KBD_CTLSTS_OBF 0x1
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#define SMCFDC37B78X_KBD_SELFTEST_PASS 0x55
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#define SMCFDC37B78X_KBD_IFCTEST_PASS 0x00
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#define SMCFDC37B78X_KBD_IRQ_KSC_EN 0xD3
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#define SMCFDC37B78X_KBD_DELAY() sysWait()
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#define SMCFDC37B78X_KBD_RD_DATA() (SMCFDC37B78X_KBD_DELAY(), \
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sysInByte (SMCFDC37B78X_KBD_DATA))
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#define SMCFDC37B78X_KBD_RD_CTLSTS() (SMCFDC37B78X_KBD_DELAY(), \
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sysInByte (SMCFDC37B78X_KBD_CTLSTS))
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#define SMCFDC37B78X_KBD_WRT_DATA(x) (SMCFDC37B78X_KBD_DELAY(), \
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sysOutByte (SMCFDC37B78X_KBD_DATA, x))
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#define SMCFDC37B78X_KBD_WRT_CTLSTS(x) (SMCFDC37B78X_KBD_DELAY(), \
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sysOutByte (SMCFDC37B78X_KBD_CTLSTS, x))
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/* typedefs */
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typedef struct smcFdc37b78x_IoPorts
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{
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int config;
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int index;
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int data;
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} SMCFDC37B78X_IOPORTS;
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/* function declarations */
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extern VOID smcFdc37b78xDevCreate (SMCFDC37B78X_IOPORTS *fdc37b78x_iop);
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extern VOID smcFdc37b78xInit (int devInitMask);
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extern STATUS smcFdc37b78xKbdInit (VOID);
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* INCsmcfdc37b78xh */
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