123 lines
4.9 KiB
C
123 lines
4.9 KiB
C
/* 403gaSerial.h - 403ga on chip serial i/o header */
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/* Copyright 1984-1995 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01b,02feb95,yao added _SPLS_RX_ERR.
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01a,02sep94,yao written.
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*/
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#ifndef __INC403gaSerialh
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#define __INC403gaSerialh
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* memory mapped i/o registers */
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#define _PPC403GA_SPLS 0x40000000 /* line status register read/clear */
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#define _PPC403GA_SPHS 0x40000002 /* handshake status register r/clear */
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#define _PPC403GA_BRDH 0x40000004 /* baudrate divisor high reg r/w */
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#define _PPC403GA_BRDL 0x40000005 /* baudrate divisor low reg r/w */
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#define _PPC403GA_SPCTL 0x40000006 /* control register r/w */
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#define _PPC403GA_SPRC 0x40000007 /* receiver command register r/w */
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#define _PPC403GA_SPTC 0x40000008 /* transmitter command register r/w */
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#define _PPC403GA_SPRB 0x40000009 /* receive buffer r */
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#define _PPC403GA_SPTB 0x40000009 /* transmit buffer w */
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/* masks and definitions for serial port control register */
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#define _SPCTL_LM_MASK 0xc0 /* loop back modes */
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#define _SPCTL_DTR_MASK 0x20 /* data terminal ready 0-inactive */
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#define _SPCTL_RTS_MASK 0x10 /* request to send 0-inactive */
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#define _SPCTL_DB_MASK 0x08 /* data bits mask */
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#define _SPCTL_PE_MASK 0x04 /* parity enable */
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#define _SPCTL_PTY_MASK 0x02 /* parity */
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#define _SPCTL_SB_MASK 0x01 /* stop bit mask */
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#define _SPCTL_LM_NORM 0x00 /* normal operation */
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#define _SPCTL_LM_LOOP 0x40 /* internal loopback mode */
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#define _SPCTL_LM_ECHO 0x80 /* automatic echo mode */
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#define _SPCTL_LM_RES 0xc0 /* reserved */
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#define _SPCTL_DTR_ACTIVE _SPCTL_DTR_MASK /* DTR is active */
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#define _SPCTL_RTS_ACTIVE _SPCTL_RTS_MASK /* RTS is active */
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#define _SPCTL_DB_8_BITS _SPCTL_DB_MASK /* 8 data bits */
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#define _SPCTL_DB_7_BITS 0x00 /* 7 data bits */
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#define _SPCTL_PE_ENABLE _SPCTL_PE_MASK /* parity enabled */
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#define _SPCTL_PTY_EVEN 0x00 /* even parity */
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#define _SPCTL_PTY_ODD _SPCTL_PTY_MASK /* odd parity */
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#define _SPCTL_SB_1_BIT 0x00 /* one stop bit */
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#define _SPCTL_SB_2_BIT _SPCTL_SB_MASK /* two stop bit */
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/* serial port handshake register */
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#define _SPHS_DIS_MASK 0x80 /* DSR input inactive error mask */
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#define _SPHS_CS_MASK 0x40 /* CTS input inactive error mask */
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#define _SPHS_DIS_ACT 0x00 /* dsr input is active */
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#define _SPHS_DIS_INACT _SPHS_DIS_MASK /* dsr input is inactive */
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#define _SPHS_CS_ACT 0x00 /* cts input is active */
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#define _SPHS_CS_INACT _SPHS_CS_MASK /* cts input is active */
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/* serial port line status register */
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#define _SPLS_RBR_MASK 0x80 /* receive buffer ready mask */
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#define _SPLS_FE_MASK 0x40 /* framing error */
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#define _SPLS_OE_MASK 0x20 /* overrun error */
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#define _SPLS_PE_MASK 0x10 /* parity error */
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#define _SPLS_LB_MASK 0x08 /* line break */
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#define _SPLS_TBR_MASK 0x04 /* transmit buffer ready */
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#define _SPLS_TSR_MASK 0x02 /* transmit shift register ready */
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#define _SPLS_RBR_FULL _SPLS_RBR_MASK /* receive buffer is full */
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#define _SPLS_FE_ERROR _SPLS_FE_MASK /* framing error detected */
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#define _SPLS_OE_ERROR _SPLS_OE_MASK /* overrun error detected */
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#define _SPLS_PE_ERROR _SPLS_PE_MASK /* parity error detected */
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#define _SPLS_LB_BREAK _SPLS_LB_MASK /* line break detected */
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#define _SPLS_TBR_EMPTY _SPLS_TBR_MASK /* transmit buffer is ready */
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#define _SPLS_TSR_EMPTY _SPLS_TSR_MASK /* transmit shift register is empty */
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#define _SPLS_RX_ERR (_SPLS_LB_BREAK | _SPLS_FE_MASK | _SPLS_OE_MASK | \
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_SPLS_PE_MASK)
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/* serial port reciever command register */
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#define _SPRC_ER_MASK 0x80 /* enable receiver mask */
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#define _SPRC_DME_MASK 0x60 /* dma mode */
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#define _SPRC_EIE_MASK 0x10 /* error interrupt enable mask */
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#define _SPRC_PME_MASK 0x08 /* pause mode mask */
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#define _SPRC_ER_ENABLE _SPRC_ER_MASK /* receiver enabled */
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#define _SPRC_DME_DISABLE 0x00 /* dma disabled */
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#define _SPRC_DME_RXRDY 0x20 /* dma disabled, RxRDY interrupt enabled */
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#define _SPRC_DME_ENABLE2 0x40 /* dma enabled,receiver src channel 2 */
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#define _SPRC_DME_ENABLE3 0x60 /* dma enabled,receiver src channel 3 */
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#define _SPRC_PME_HARD _SPRC_PME_MASK /* RTS controlled by hardware */
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#define _SPRC_PME_SOFT 0x00 /* RTS controlled by software */
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/* serial port transmit command register */
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#define _SPTC_ET_MASK 0x80 /* transmiter enable mask */
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#define _SPTC_DME_MASK 0x60 /* dma mode mask */
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#define _SPTC_TIE_MASK 0x10 /* empty interrupt enable mask */
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#define _SPTC_EIE_MASK 0x08 /* error interrupt enable mask */
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#define _SPTC_SPE_MASK 0x04 /* stop/pause mask */
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#define _SPTC_TB_MASK 0x02 /* transmit break mask */
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#define _SPTC_ET_ENABLE _SPTC_ET_MASK /* transmiter enabled */
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#define _SPTC_DME_DISABLE 0x00 /* transmiter disabled, TBR intr disabled */
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#define _SPTC_DME_TBR 0x20 /* transmiter disabled, TBR intr enabled */
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#define _SPTC_DME_CHAN_2 0x40 /* dma enabled, destination chann 2 */
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#define _SPTC_DME_CHAN_3 0x60 /* dma enabled, destination chann 3 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INC403gaSerialh */
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