291 lines
8.6 KiB
C
291 lines
8.6 KiB
C
/* octeonBoard.h - Board configuration file */
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/*
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* Copyright (c) 2008-2011 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01j,20dec11,x_f Add CN68XX board type
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01i,05jan11,d_c Defect WIND00249323 Fix WIND00249325 - configure PCIe bus
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01h,09nov10,d_c Remove definition of OCTEON_CACHE_ALIGN_SIZE.
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It's redundant with respect to CVMX_CACHE_LINE_SIZE
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in octeonMips64.h
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01g,04sep10,d_c Change CFG_I2C_EEPROM_ADDR for 63xx
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01f,31aug10,rlg addition of cn63xx defines
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01e,26aug10,pgh Removed octeon-model.h
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01d,09mar09,j_z add macros for 56xx and normalize file header
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01c,24sep08,pgh Fix copyright.
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01b,12jul08,l_z add macros for 50xx and normalize file header
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01a,14may08,l_z add macros for 58xx and normalize file header
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DESCRIPTION
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*/
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#ifndef OCTEON_BOARD_H
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#define OCTEON_BOARD_H
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#define CONFIG_OCTEON 1
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#define CAVIUM_BOARD_EBH3010 1
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#define CAVIUM_BOARD_EBH3100 2
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#define CAVIUM_BOARD_EBT3000 3
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#define CAVIUM_BOARD_EBH50XX 4
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#define CAVIUM_BOARD_EBH5020 5
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#define CAVIUM_BOARD_EVB5860 6
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#define CAVIUM_BOARD_EBH5600 7
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#define CAVIUM_BOARD_EVB6300 8
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#define CAVIUM_BOARD_EVB6800 9
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#define CAVIUM_BOARD_EBB7800 10
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#define CPU_CLOCK_RATE (cavCpuClockRateGet())
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#if OCTEON_BOARD == CAVIUM_BOARD_EBT3000
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#define BOARD_REV_MAJOR 3
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#define BOARD_REV_MINOR 1
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#define DEFAULT_CPU_CLOCK_RATE 500000000
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#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
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#define CFG_ATA_DATA_OFFSET 0x400
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#define CFG_ATA_REG_OFFSET 0
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_I2C_EEPROM_ADDR 0x52
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#endif /* OCTEON_BOARD == CAVIUM_BOARD_EBT3000 */
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#if OCTEON_BOARD == CAVIUM_BOARD_EBH3010
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#define BOARD_REV_MINOR 0
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#define BOARD_REV_MAJOR 1
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#define DEFAULT_CPU_CLOCK_RATE 500000000
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#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
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#define CFG_ATA_DATA_OFFSET 0x400
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#define CFG_ATA_REG_OFFSET 0
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_I2C_EEPROM_ADDR 0x56
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#endif /* OCTEON_BOARD == CAVIUM_BOARD_EBH3010 */
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#if OCTEON_BOARD == CAVIUM_BOARD_EBH3100
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#define BOARD_REV_MINOR 0
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#define BOARD_REV_MAJOR 1
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#define DEFAULT_CPU_CLOCK_RATE 500000000
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#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
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#define CFG_ATA_DATA_OFFSET 0x400
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#define CFG_ATA_REG_OFFSET 0
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_I2C_EEPROM_ADDR 0x56
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#endif /* OCTEON_BOARD == CAVIUM_BOARD_EBH3100 */
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#if OCTEON_BOARD == CAVIUM_BOARD_EBH50XX
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#define BOARD_REV_MINOR 0
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#define BOARD_REV_MAJOR 1
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#define DEFAULT_CPU_CLOCK_RATE 400000000
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#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
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#define CFG_ATA_DATA_OFFSET 0x400
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#define CFG_ATA_REG_OFFSET 0
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_I2C_EEPROM_ADDR 0x56
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#endif /* OCTEON_MODEL == OCTEON_CN50XX */
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#if OCTEON_BOARD == CAVIUM_BOARD_EBH5020
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#define BOARD_REV_MINOR 0
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#define BOARD_REV_MAJOR 1
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#define DEFAULT_CPU_CLOCK_RATE 400000000
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#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
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#define CFG_ATA_DATA_OFFSET 0x400
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#define CFG_ATA_REG_OFFSET 0
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_I2C_EEPROM_ADDR 0x56
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#define PCI_IO_ADRS 0x00001000
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#define PCI_IO_SIZE 0x08000000
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#define PCI_IO16_SIZE 0x0
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#define PCI_MEM_ADRS 0x80000000
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#define PCI_MEM_SIZE 0x40000000
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#define OCTEON_PCI_LAT_TIMER 0xff
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#define I2C_RTC_ADDR (0x68)
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#endif /* OCTEON_BOARD == OCTEON_CN5020 */
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#if OCTEON_BOARD == CAVIUM_BOARD_EBH5600
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#define BOARD_REV_MAJOR 1
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#define BOARD_REV_MINOR 1
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#define DEFAULT_CPU_CLOCK_RATE 800000000
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#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
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#define CFG_ATA_DATA_OFFSET 0x400
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#define CFG_ATA_REG_OFFSET 0
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_I2C_EEPROM_ADDR 0x56
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#define PCIE0_IO_ADRS 0x00001000
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#define PCIE0_IO_SIZE 0x04000000
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#define PCIE0_MEM_ADRS 0x80000000
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#define PCIE0_MEM_SIZE 0x20000000
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#define PCIE1_IO_ADRS (PCIE0_IO_ADRS + PCIE0_IO_SIZE)
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#define PCIE1_IO_SIZE PCIE0_IO_SIZE
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#define PCIE1_MEM_ADRS (PCIE0_MEM_ADRS + PCIE0_MEM_SIZE)
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#define PCIE1_MEM_SIZE PCIE0_MEM_SIZE
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#define I2C_RTC_ADDR (0x68)
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#endif /* OCTEON_BOARD == CAVIUM_BOARD_EBH5600 */
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#if OCTEON_BOARD == CAVIUM_BOARD_EVB5860
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#define BOARD_REV_MAJOR 3
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#define BOARD_REV_MINOR 1
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#define DEFAULT_CPU_CLOCK_RATE 800000000
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#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
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#define CFG_ATA_DATA_OFFSET 0x400
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#define CFG_ATA_REG_OFFSET 0
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_I2C_EEPROM_ADDR 0x52
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#define I2C_RTC_ADDR (0x68)
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#endif /* OCTEON_BOARD == CAVIUM_BOARD_EVB5860 */
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#if OCTEON_BOARD == CAVIUM_BOARD_EVB6300
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#define BOARD_REV_MAJOR 1
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#define BOARD_REV_MINOR 0
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#define DEFAULT_CPU_CLOCK_RATE 800000000
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#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
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#define CFG_ATA_DATA_OFFSET 0x400
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#define CFG_ATA_REG_OFFSET 0
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_I2C_EEPROM_ADDR 0x56
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#define PCIE0_IO_ADRS 0x00001000
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#define PCIE0_IO_SIZE 0x04000000 /* 64M */
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#define PCIE0_MEM_ADRS 0x80000000
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#define PCIE0_MEM_SIZE 0x20000000 /* 512M */
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#define PCIE1_IO_ADRS (PCIE0_IO_ADRS + PCIE0_IO_SIZE)
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#define PCIE1_IO_SIZE PCIE0_IO_SIZE
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#define PCIE1_MEM_ADRS (PCIE0_MEM_ADRS + PCIE0_MEM_SIZE)
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#define PCIE1_MEM_SIZE PCIE0_MEM_SIZE
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#define I2C_RTC_ADDR (0x68)
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#endif /* OCTEON_BOARD == CAVIUM_BOARD_EVB6300 */
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#if OCTEON_BOARD == CAVIUM_BOARD_EVB6800
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#define BOARD_REV_MAJOR 1
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#define BOARD_REV_MINOR 0
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#define DEFAULT_CPU_CLOCK_RATE 800000000
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#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
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#define CFG_ATA_DATA_OFFSET 0x400
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#define CFG_ATA_REG_OFFSET 0
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_I2C_EEPROM_ADDR 0x56
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#define I2C_RTC_ADDR (0x68)
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#endif /* OCTEON_BOARD == CAVIUM_BOARD_EVB6800 */
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#if OCTEON_BOARD == CAVIUM_BOARD_EBB7800
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#define BOARD_REV_MAJOR 1
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#define BOARD_REV_MINOR 0
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#define DEFAULT_CPU_CLOCK_RATE 1600000000
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define PCIE0_IO_ADRS 0x00001000
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#define PCIE0_IO_SIZE 0x04000000 /* 64M */
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#define PCIE0_MEM_ADRS 0x80000000
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#define PCIE0_MEM_SIZE 0x10000000 /* 256M */
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#define PCIE1_IO_ADRS (PCIE0_IO_ADRS + PCIE0_IO_SIZE)
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#define PCIE1_IO_SIZE PCIE0_IO_SIZE
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#define PCIE1_MEM_ADRS (PCIE0_MEM_ADRS + PCIE0_MEM_SIZE)
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#define PCIE1_MEM_SIZE PCIE0_MEM_SIZE
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#define PCIE2_IO_ADRS (PCIE1_IO_ADRS + PCIE1_IO_SIZE)
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#define PCIE2_IO_SIZE PCIE1_IO_SIZE
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#define PCIE2_MEM_ADRS (PCIE1_MEM_ADRS + PCIE1_MEM_SIZE)
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#define PCIE2_MEM_SIZE PCIE1_MEM_SIZE
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#define PCIE3_IO_ADRS (PCIE2_IO_ADRS + PCIE2_IO_SIZE)
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#define PCIE3_IO_SIZE PCIE2_IO_SIZE
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#define PCIE3_MEM_ADRS (PCIE2_MEM_ADRS + PCIE2_MEM_SIZE)
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#define PCIE3_MEM_SIZE PCIE2_MEM_SIZE
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#define CFG_I2C_EEPROM_ADDR 0x56
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#endif /* OCTEON_BOARD == CAVIUM_BOARD_EBB7800 */
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
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#define PHYS_FLASH_1 0xbf400000 /* Flash Bank #1 */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (192 << 10)
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#define CFG_INIT_SP_OFFSET 0x400000
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#define CFG_FLASH_BASE PHYS_FLASH_1
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#define CFG_FLASH_PROTECT_LEN 0x80000 /* protect low 512K */
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#define CFG_FLASH_CFI 1
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#define CFG_FLASH_CFI_DRIVER 1
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#endif /* OCTEON_BOARD_H */
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