119 lines
3.6 KiB
C
119 lines
3.6 KiB
C
/* archMipsCommon.h - common Mips architecture specific header */
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/*
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* Copyright (c) 2003-2004, 2006-2007, 2012 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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* This file has been developed or significantly modified by the
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* MIPS Center of Excellence Dedicated Engineering Staff.
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* This notice is as per the MIPS Center of Excellence Master Partner
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* Agreement, do not remove this notice without checking first with
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* WR/Platforms MIPS Center of Excellence engineering management.
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*/
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/*
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modification history
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--------------------
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01o,21mar12,jpb Updated for POSIX namespace isolation conformance (part of
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defect Defect WIND000307800).
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01n,09aug07,pad _VX_CPU_MIPS_64BIT and _VX_CPU_MIPS_32BIT were not defined
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when _POSIX_C_SOURCE was defined by the applications. This is
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now fixed.
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01m,11jul07,zl added _WRS_CPU_HAS_CLZ_INSTR.
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01l,04may07,zl updated portable library build configuration.
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01k,21feb07,pes Add support for new MIPS lib structure.
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01j,26jun06,jpb Updated for POSIX namespace conformance.
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Changed C preprocessor macro CPU to _VX_CPU.
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01i,02feb06,mil Updated for POSIX namespace conformance.
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01h,30sep04,pes added define of _WRS_NO_BITS_PHYS_ADDR
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01g,01oct04,tam moved definition of _TYPE_PHYS_ADDR to the kernel
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architecture scpecific header
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01f,17sep04,pes moved _TYPE_PHYS_ADDDR and _WRS_PHYS_ADDR_IS_64_BITS here
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from archMips.h
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01e,22mar04,zl moved trcLib_PORTABLE, _RType and INSTR definitions here.
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01d,17mar04,pes Enable Coprocessor Abstraction
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01c,25nov03,pes Moved definition of _BYTE_ORDER to archMipsCommon.h.
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01b,12nov03,job Moved some blib stuff from archMips.h
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01a,11nov03,pes written.
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*/
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#ifndef __INCarchMipsCommonh
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#define __INCarchMipsCommonh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(MIPSEB) || defined(__MIPSEB__)
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#undef _BYTE_ORDER
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#define _BYTE_ORDER _BIG_ENDIAN
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#elif defined(MIPSEL) || defined(__MIPSEL__)
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#undef _BYTE_ORDER
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#define _BYTE_ORDER _LITTLE_ENDIAN
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#else
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#warning "One of MIPSEL or MIPSEB must be defined"
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#endif
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#define _WRS_PAL_COPROC_LIB /* enable coprocessor abstraction */
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/* from bLib.c */
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#define _WRS_BLIB_ALIGNMENT 3 /* quad byte alignment mask */
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/*
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* CLZ instruction (used for ffsMsb and ffsLsb) not supported
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* by MIPSI2 and MIPSI3
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*
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* IMPORTANT: this must be conditional on ISA level, and not variant level
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*/
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#if (_VX_CPU != _VX_MIPSI2) && (_VX_CPU != _VX_MIPSI3)
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#define _WRS_CPU_HAS_CLZ_INSTR
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#endif /* !_VX_MIPSI2 && !_VX_MIPSI3 */
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/* 32/64 bit */
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#define _VX_CPU_MIPS_32BIT ((_VX_CPU==_VX_MIPS32) || \
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(_VX_CPU==_VX_MIPSI2) || \
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(_VX_CPU==_VX_MIPSI32) || \
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(_VX_CPU==_VX_MIPSI32R2))
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#define _VX_CPU_MIPS_64BIT ((_VX_CPU==_VX_MIPS64) || \
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(_VX_CPU==_VX_MIPSI3) || \
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(_VX_CPU==_VX_MIPSI64) || \
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(_VX_CPU==_VX_MIPSI64R2))
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#ifndef _ASMLANGUAGE
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typedef unsigned long _Vx_INSTR; /* 32 bit word-aligned instructions */
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#if !defined(_POSIX_C_SOURCE) && !defined(_XOPEN_SOURCE) && \
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!defined(_POSIX_AEP_RT_CONTROLLER_C_SOURCE)
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typedef _Vx_INSTR INSTR;
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#endif /* !_POSIX_xxx_SOURCE */
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#if (_VX_CPU_MIPS_32BIT)
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typedef unsigned long _RType; /* registers are 32 bits */
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#elif (_VX_CPU_MIPS_64BIT)
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typedef unsigned long long _RType; /* registers are 64 bits */
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#else /* _VX_CPU_MIPSxxBIT */
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#error "Invalid CPU value"
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#endif /* _VX_CPU */
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#endif /* !_ASMLANGUAGE */
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#define _WRS_NO_BITS_PHYS_ADDR 64
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCarchMipsCommonh */
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