134 lines
3.6 KiB
C
134 lines
3.6 KiB
C
/* vxAtomicArchLib.h - PowerPC specific atomic library header */
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/*
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* Copyright (c) 2006-2010 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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modification history
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--------------------
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01k,27dec10,lzh remove the warning of vxAtomicGet_inline when
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compiled with gnu.
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01j,29apr10,pad Moved extern C statement after include statements.
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01i,15may09,gls made memory barriers available in user space
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01i,28apr09,cww Add fixed size APIs
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01h,27aug08,jpb Renamed VSB header file
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01g,24jun08,jpb Added include path for kernel configurations options set in
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vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
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01f,16jun08,zl use _WRS_BARRIER() for memory barrier implementations
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01e,07mar08,to add vxAtomicGet_inline as macro; fix vxCas for UP
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01d,17jan08,gls renamed inline routines
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01c,14dec07,gls added _inline_vxCas()
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01b,22nov06,mmi switch lwsync to sync
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01a,17nov06,mmi add Created
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*/
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#ifndef __INCvxAtomicArchLibh
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#define __INCvxAtomicArchLibh
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#include <arch/ppc/vxAtomicArchLibCommon.h>
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#ifndef _ASMLANGUAGE
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#include <vsbConfig.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined (__DCC__)
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#ifdef _WRS_CONFIG_SMP
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#define vxCas_inline vxAtomicCas_inline
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__asm volatile BOOL vxAtomicCas_inline (atomic_t * address, atomicVal_t old_value,
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atomicVal_t new_value)
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{
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% reg address; reg old_value; reg new_value; \
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lab vxCas_inline_again; lab vxCasErr_inline; lab vxCasDone_inline
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! "r6"
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vxCas_inline_again:
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lwarx r6, 0, address /* load and reserve */
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cmpw r6, old_value /* operands equal */
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bne- vxCasErr_inline /* skip if not */
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stwcx. new_value, 0, address /* store new value if still reserved */
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bne- vxCas_inline_again /* loop if lost reservation */
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li r3, 1 /* cmp and swap successful, return 1 */
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b vxCasDone_inline
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vxCasErr_inline:
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li r3, 0 /*cmp and swap failed, return 0 */
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vxCasDone_inline:
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}
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__asm volatile BOOL vxAtomic32Cas_inline (atomic32_t * address, atomic32Val_t old_value,
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atomic32Val_t new_value)
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{
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% reg address; reg old_value; reg new_value; \
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lab vxCas_inline_again; lab vxCasErr_inline; lab vxCasDone_inline
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! "r6"
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vxCas_inline_again:
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lwarx r6, 0, address /* load and reserve */
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cmpw r6, old_value /* operands equal */
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bne- vxCasErr_inline /* skip if not */
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stwcx. new_value, 0, address /* store new value if still reserved */
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bne- vxCas_inline_again /* loop if lost reservation */
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li r3, 1 /* cmp and swap successful, return 1 */
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b vxCasDone_inline
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vxCasErr_inline:
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li r3, 0 /*cmp and swap failed, return 0 */
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vxCasDone_inline:
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}
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#else /* _WRS_CONFIG_SMP */
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#define vxCas_inline vxAtomicCas
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#define vxAtomicCas_inline vxAtomicCas
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#define vxAtomic32Cas_inline vxAtomic32Cas
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#endif /* _WRS_CONFIG_SMP */
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#elif defined (__GNUC__)
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#define vxCas_inline vxAtomicCas
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#define vxAtomicCas_inline vxAtomicCas
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#define vxAtomic32Cas_inline vxAtomic32Cas
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#else
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#define vxCas_inline vxAtomicCas
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#define vxAtomicCas_inline vxAtomicCas
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#define vxAtomic32Cas_inline vxAtomic32Cas
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#endif /* _VX_TOOL_FAMILY */
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#if defined (__DCC__)
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#define vxAtomic32Get_inline(target) \
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((atomic32Val_t)(*(volatile atomic32_t *)(target)))
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#elif defined (__GNUC__)
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#define vxAtomic32Get_inline vxAtomicGet
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#else
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#define vxAtomic32Get_inline vxAtomicGet
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#endif
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#define vxAtomicGet_inline vxAtomic32Get_inline
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCvxAtomicArchLibh */
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