203 lines
5.5 KiB
C
203 lines
5.5 KiB
C
/* quiccIntrCtl.h - PowerQuicc interrupt controller header file */
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/* Copyright (c) 2005-2007 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01c,05sep07,dtr WIND0045894 - INUM_CPIO1 to INUM_GPIO1.
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01b,09may06,dtr Add 8360 support.
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01a,10jan05,dtr adapted from m85xxIntrCtl.
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*/
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#ifndef __INCquiccIntrCtlh
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#define __INCquiccIntrCtlh
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#include "vxWorks.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef _ASMLANGUAGE
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#define CAST(x)
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#else /* _ASMLANGUAGE */
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#define CAST(x) (x)
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#endif /* _ASMLANGUAGE */
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#ifdef IVEC_TO_INUM
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# undef IVEC_TO_INUM
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#endif /* IVEC_TO_INUM */
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#ifdef INUM_TO_IVEC
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# undef INUM_TO_IVEC
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#endif /* INUM_TO_IVEC */
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#define IVEC_TO_INUM(intVec) (quiccIvecToInum(intVec))
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#define INUM_TO_IVEC(intNum) (quiccInumToIvec(intNum))
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#ifdef PQ2PRO
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#define INUM_UART1 9
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#define INUM_UART2 10
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#define INUM_SEC 11
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#define INUM_I2C1 14
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#define INUM_I2C2 15
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#define INUM_SPI 16
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#define INUM_IRQ1 17
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#define INUM_IRQ2 18
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#define INUM_IRQ3 19
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#define INUM_IRQ4 20
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#define INUM_IRQ5 21
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#define INUM_IRQ6 22
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#define INUM_IRQ7 23
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#define INUM_TSEC1_TX 32
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#define INUM_TSEC1_RX 33
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#define INUM_TSEC1_ERR 34
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#define INUM_TSEC2_TX 35
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#define INUM_TSEC2_RX 36
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#define INUM_TSEC2_ERR 37
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#define INUM_USB2_DR 38
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#define INUM_USB2_MPH 39
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#define INUM_IRQ0 48
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#define INUM_RTC_SEC 64
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#define INUM_PIT 65
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#define INUM_PCI1 66
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#define INUM_PCI2 67
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#define INUM_RTC_ALR 68
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#define INUM_MU 69
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#define INUM_SBA 70
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#define INUM_DMA 71
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#define INUM_GTM4 72
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#define INUM_GTM8 73
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#define INUM_GPIO1 74
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#define INUM_GPIO2 75
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#define INUM_DDR 76
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#define INUM_LBC 77
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#define INUM_GTM2 78
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#define INUM_GTM6 79
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#define INUM_PMC 80
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#define INUM_GTM3 84
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#define INUM_GTM7 85
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#define INUM_GTM1 90
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#define INUM_GTM5 91
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#define INUM_MAX 128
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#define IVEC_MAX 128
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#endif
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#ifdef PQ2PRO_QE
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#define INUM_UART1 9
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#define INUM_UART2 10
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#define INUM_SEC 11
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#define INUM_I2C1 14
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#define INUM_I2C2 15
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#define INUM_IRQ1 17
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#define INUM_IRQ2 18
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#define INUM_IRQ3 19
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#define INUM_IRQ4 20
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#define INUM_IRQ5 21
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#define INUM_IRQ6 22
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#define INUM_IRQ7 23
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#define INUM_QE_HIGH 32
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#define INUM_QE_LOW 33
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#define INUM_IRQ0 48
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#define INUM_RTC_SEC 64 /* ??? */
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#define INUM_PIT 65 /* ??? */
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#define INUM_PCI1 66
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#define INUM_RTC_ALR 68
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#define INUM_MU 69
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#define INUM_SBA 70
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#define INUM_DMA 71
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#define INUM_GTM4 72
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#define INUM_GTM8 73
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#define INUM_QE_PORTS 74
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#define INUM_SDDR 75
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#define INUM_DDR 76
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#define INUM_LBC 77
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#define INUM_GTM2 78
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#define INUM_GTM6 79
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#define INUM_PMC 80
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#define INUM_GTM3 84
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#define INUM_GTM7 85
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#define INUM_GTM1 90
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#define INUM_GTM5 91
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#define INUM_MAX 128
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#define IVEC_MAX 128
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#endif
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/* Interrupt Controller Registers */
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#define QUICC_SICR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x000))
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#define QUICC_SIVEC(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x004))
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#define QUICC_SIPNR_H(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x008))
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#define QUICC_SIPNR_L(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x00C))
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#define QUICC_SIPRR_A(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x010))
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#define QUICC_SIPRR_D(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x01C))
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#define QUICC_SIMR_H(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x020))
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#define QUICC_SIMR_L(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x024))
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#define QUICC_SICNR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x028))
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#define QUICC_SEPNR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x02C))
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#define QUICC_SMPRR_A(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x030))
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#define QUICC_SMPRR_B(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x034))
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#define QUICC_SEMSR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x038))
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#define QUICC_SECNR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x03C))
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#define QUICC_SERSR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x040))
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#define QUICC_SERMR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x044))
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#define QUICC_SERCR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x048))
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#define QUICC_SIFCR_H(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x050))
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#define QUICC_SIFCR_L(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x054))
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#define QUICC_SEFCR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x058))
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#define QUICC_SERFR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x05C))
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#define QUICC_SCVCR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x060))
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#define QUICC_SMVCR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x064))
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/* interrupt handler */
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#ifndef _ASMLANGUAGE
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typedef struct intr_handler
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{
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VOIDFUNCPTR vec; /* interrupt vector */
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int arg; /* interrupt handler argument */
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void *pNext;
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} INTR_HANDLER;
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/* function declarations */
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#if defined(__STDC__) || defined(__cplusplus)
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IMPORT STATUS quiccIntrInit ();
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extern STATUS quiccIntDisable (int );
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IMPORT STATUS quiccIntEnable (int );
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extern int quiccIvecToInum(VOIDFUNCPTR *);
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extern VOIDFUNCPTR * quiccInumToIvec(int);
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#else
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IMPORT STATUS quiccIntrInit ();
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extern STATUS quiccIntDisable ();
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IMPORT STATUS quiccIntEnable ();
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extern int quiccIvecToInum();
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extern VOIDFUNCPTR * quiccInumToIvec();
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#endif /* __STDC__ */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCquiccIntrCtlh */
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