382 lines
18 KiB
C
382 lines
18 KiB
C
/* elt3c509End.h - 3Com EtherLink III END network interface header*/
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/* Copyright 1998-2000, 2010 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01e,29apr10,pad Moved extern C statement after include statements.
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01d,02aug00,jkf moved statistic definitions to the driver, SPR#26952
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01c,11jun00,ham removed reference to etherLib.
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01b,10mar99,sbs added DEF_NUM_RX_FRAMES.
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01a,28sep98,snk written by mBedded Innovations Inc.
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*/
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#ifndef __INCelt3c509Endh
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#define __INCelt3c509Endh
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#include "netinet/if_ether.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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/* debug defines */
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#undef DRV_DEBUG
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#ifdef DRV_DEBUG
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#define ELT_TIMING
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#endif /* DRV_DEBUG */
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/* defines */
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#define EA_SIZE 6 /* one Ethernet address */
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#define EH_SIZE 14 /* ethernet header size */
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#define MAX_FRAME_SIZE (EH_SIZE + ETHERMTU) /* capacity of buffer */
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#define DEF_NUM_RX_FRAMES 64 /* default number of receive frames */
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#define ATTACHMENT_DEFAULT 0 /* use card as configured */
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#define ATTACHMENT_AUI 1 /* AUI (thick, DIX, DB-15) */
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#define ATTACHMENT_BNC 2 /* BNC (thin, 10BASE-2) */
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#define ATTACHMENT_RJ45 3 /* RJ-45 (twisted pair, TPE,10BASE-T)*/
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/* Configuration items */
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#define ELT3C509_BUFSIZ (ETHERMTU + SIZEOF_ETHERHEADER + 6)
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#define ELT3C509_SPEED 10000000
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#define ELT_PRODUCTID_3C589 0x9058 /* product ID for PCMCIA 3C589 */
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/* naming items */
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#define ELT3C509_DEV_NAME "elt"
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#define ELT3C509_DEV_NAME_LEN 4
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/* flags */
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#define ELT3C_PROMISCUOUS_FLAG 0x1
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#define ELT3C_RCV_HANDLING_FLAG 0x2
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#define ELT3C_POLLING 0x4
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/* statistic block, see also driver source code */
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typedef struct
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{
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#ifdef ELT_TIMING
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UINT elt3c509Stats[40];
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#else
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UINT elt3c509Stats[30];
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#endif
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} ELT3C509_STAT;
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/* ELT driver data structures */
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typedef struct elt3c509_device
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{
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END_OBJ endObj; /* The class we inherit from. */
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int unit; /* unit number */
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char * pTxCluster; /* pointer to transmit cluster */
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int nRxFrames; /* number of recv frames */
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int rxFilter; /* current recv address filter bits */
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int port; /* base I/O port of this board */
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int ivec; /* interrupt vector */
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int intLevel; /* interrupt level */
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int attachment; /* connector to use (AUI,BNC,TPE) */
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int intMask; /* current board interrupt mask */
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ELT3C509_STAT elt3c509Stat; /* statistics */
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long flags; /* Our local flags. */
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UCHAR enetAddr [6]; /* ethernet address */
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CACHE_FUNCS cacheFuncs; /* cache function pointers */
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BOOL txBlocked; /* indicates netTask active/queued */
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CL_POOL_ID pClPoolId; /* cluster pool id */
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M_CL_CONFIG endClConfig; /* cluster config structure */
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CL_DESC endClDesc; /* cluster descriptor table */
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#ifdef ELT_TIMING
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int interruptTime; /* timer value at ISR, -1 if invalid */
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int maxRxLatency; /* max time to service receive buffer */
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#endif /* ELT_TIMING */
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} ELT3C509_DEVICE;
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/* ELT register offsets, grouped by window number */
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/* all windows */
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#define ELT3C509_COMMAND 0x0e /* command register */
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#define ELT3C509_STATUS 0x0e /* status register */
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/* window number symbols for selection command */
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#define WIN_CONFIG 0x0000
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#define WIN_OPERATING 0x0001
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#define WIN_ADDRESS 0x0002
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#define WIN_FIFO 0x0003
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#define WIN_DIAGNOSTIC 0x0004
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#define WIN_RESULTS 0x0005
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#define WIN_STATISTICS 0x0006
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/* window 0, configuration and EEPROM */
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#define MANUF_ID 0x00 /* manufacturer ID */
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#define PRODUCT_ID 0x02 /* product ID/MCA adapter ID */
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#define CONFIG_CONTROL 0x04 /* configuration control */
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#define ADDRESS_CONFIG 0x06 /* address configuration */
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#define RESOURCE_CONFIG 0x08 /* resource configuration */
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#define EEPROM_CONTROL 0x0a /* EEPROM control */
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#define EEPROM_DATA 0x0c /* EEPROM data in/out */
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/* window 1, operating set */
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#define DATA_REGISTER 0x00 /* data (low word) in/out */
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#define DATA_HIGH 0x02 /* data (high word) in/out */
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#define RX_STATUS 0x08 /* received packet status */
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#define TIMER 0x0a /* (byte) interrupt latency timer */
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#define TX_STATUS 0x0b /* (byte) transmit status */
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#define TX_FREE_BYTES 0x0c /* free bytes available in tx FIFO */
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/* also appears in window 3 */
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/* window 2, station address setup/read */
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#define ADDRESS_0 0x00 /* (byte) station address 0 */
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#define ADDRESS_1 0x01 /* (byte) station address 1 */
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#define ADDRESS_2 0x02 /* (byte) station address 2 */
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#define ADDRESS_3 0x03 /* (byte) station address 3 */
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#define ADDRESS_4 0x04 /* (byte) station address 4 */
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#define ADDRESS_5 0x05 /* (byte) station address 5 */
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/* window 3, FIFO management */
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#define TX_RECLAIM 0x08 /* MCA tx reclaim threshold */
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#define RX_FREE_BYTES 0x0a /* free bytes available in rx FIFO */
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#define TX_FREE_BYTES_3 0x0c /* free bytes available in tx FIFO */
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/* also appears in window 1 */
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/* same offset so can use same macro */
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/* window 4, diagnostics */
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#define TX_DIAGNOSTIC 0x00 /* tx diagnostic */
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#define HOST_DIAGNOSTIC 0x02 /* host diagnostic */
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#define FIFO_DIAGNOSTIC 0x04 /* FIFO diagnostic */
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#define NET_DIAGNOSTIC 0x06 /* net diagnostic */
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#define ETHERNET_STATUS 0x08 /* ethernet controller status */
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#define MEDIA_STATUS 0x0a /* media type and status */
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/* window 5, command results and internal state (read only) */
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#define TX_START_THRESH 0x00 /* tx start threshold + 4 */
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#define TX_AVAIL_THRESH 0x02 /* tx available threshold */
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#define RX_EARLY_THRESH 0x06 /* rx early threshold */
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#define RX_FILTER 0x08 /* rx filter lower 4 bits */
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#define INTERRUPT_MASK 0x0a /* interrupt mask */
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#define READ_ZERO_MASK 0x0c /* read zero mask */
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/* window 6, statistics registers (byte regs. MUST be read/written as bytes) */
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#define CARRIER_LOSTS 0x00 /* (byte) carrier loss during tx */
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#define SQE_FAILURES 0x01 /* (byte) heartbeat loss during tx */
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#define MULT_COLLISIONS 0x02 /* (byte) tx with multiple collis. */
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#define ONE_COLLISIONS 0x03 /* (byte) tx with one collision */
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#define LATE_COLLISIONS 0x04 /* (byte) tx with late collision */
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#define RECV_OVERRUNS 0x05 /* (byte) receive overruns */
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#define GOOD_TRANSMITS 0x06 /* (byte) frames transmitted OK */
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#define GOOD_RECEIVES 0x07 /* (byte) frames received OK */
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#define TX_DEFERRALS 0x08 /* (byte) transmit deferrals */
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#define BYTES_RECEIVED 0x0a /* total bytes received OK */
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#define BYTES_TRANSMITTED 0x0c /* total bytes transmitted OK */
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/* ISA ID sequence state machine commands */
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#define ID_PORT 0x0100 /* I/O port to access ID sequence */
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/* could be 0x110..0x1f0 but this */
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/* is a highly unlikely address to */
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/* be used by anything else */
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#define ID_RESET 0x00 /* reset ID state machine */
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#define ID_EEPROM_READ 0x80 /* read EEPROM register addressed by */
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/* last 6 bits of this command */
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#define ID_EEPROM_MASK 0x3f /* these bits here */
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#define ID_SET_TAG 0xd0 /* set tag register to last 3 bits */
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#define ID_TAG_MASK 0x07 /* values 1..7 take tagged adapter */
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/* out of the contention process */
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#define ID_ACTIVATE 0xff /* activate adapter as pre-configured */
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#define ID_SEQUENCE_INITIAL 0xff /* initial value in ID sequence */
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#define ID_SEQUENCE_LENGTH 255 /* iteration count */
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#define ID_CARRY_BIT 0x100 /* carry out of 8-bit ID value shift */
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#define ID_POLYNOMIAL 0xcf /* XOR this with ID value */
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#define ID_REGISTER_SIZE 16 /* bits in an EEPROM register */
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/* important EEPROM addresses */
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#define EE_A_PRODUCT_ID 0x03 /* 3C5xx product id */
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#define EE_A_MANUFACTURER 0x07 /* 3Com mfg. id == 0x6d50 */
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#define EE_A_ADDRESS 0x08 /* address configuration */
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#define EE_A_RESOURCE 0x09 /* resource configuration */
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#define EE_A_OEM_NODE_0 0x0a /* word 0 of OEM Ethernet address */
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#define EE_A_OEM_NODE_1 0x0b /* word 1 of OEM Ethernet address */
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#define EE_A_OEM_NODE_2 0x0c /* word 2 of OEM Ethernet address */
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#define MANUFACTURER_ID 0x6d50 /* 3Com id code in EEPROM */
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/* address configuration register fields and values */
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#define AC_IO_BASE_MASK 0x001f /* I/O base address encoding */
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/* 0-30 select n * 0x10 + 0x200 */
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#define AC_IO_BASE_ZERO 0x0200 /* first encoded address */
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#define AC_IO_BASE_FACTOR 0x10 /* convert code to address range */
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#define AC_IO_BASE_EISA 0x001f /* EISA addressing indicator */
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#define AC_XCVR_MASK 0xc000 /* transciever selection field */
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#define AC_XCVR_TPE 0x0000 /* select twisted-pair (10BASE-T) */
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#define AC_XCVR_AUI 0x4000 /* select AUI (external transceiver) */
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#define AC_XCVR_BNC 0xc000 /* select BNC (10BASE-2); must also */
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/* activate with START_COAX command */
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/* configuration control register bits */
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#define CC_ENABLE 0x0001 /* set to enable IRQ driver */
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#define CC_RESET 0x0004 /* reset adapter to POR state */
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#define CC_POR_INTERNAL_ENDEC 0x0100 /* use internal encoder/decoder */
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#define CC_POR_10BASETAVAIL 0x0200
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/* on-board TPE transceiver available */
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#define CC_POR_TEST_MASK 0x0c00 /* test mode bits */
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#define CC_POR_TEST_RECEIVE 0x0400 /* receive test mode */
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#define CC_POR_TEST_TRANSMIT 0x0800 /* transmit test mode */
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#define CC_POR_TEST_NORMAL 0x0c00 /* normal operation mode */
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#define CC_POR_10BASE2_AVAIL 0x1000
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/* on-board coax transceiver available*/
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#define CC_POR_AUI_AVAIL 0x2000 /* on-board AUI connector evailable */
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/* FIFO diagnostic register bits */
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#define FD_TX_BC 0x0001 /* TX BIST is complete */
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#define FD_TX_BF 0x0002 /* TX BIST has failed */
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#define FD_TX_BFC 0x0004 /* sets TX BF to test for stuck-at */
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#define FD_TX_BIST 0x0008 /* enable BIST in TX FIFO RAM */
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#define FD_RX_BC 0x0010 /* TRX BIST is complete */
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#define FD_RX_BF 0x0020 /* RX BIST has failed */
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#define FD_RX_BFC 0x0040 /* sets RX BF to test for stuck-at */
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#define FD_RX_BIST 0x0080 /* enable BIST in RX FIFO RAM */
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#define FD_TX_OVERRUN 0x0400 /* host wrote too much data */
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#define FD_RX_OVERRUN 0x0800 /* RX overrun (not necessarily */
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/* packet overrun yet) */
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#define FD_RX_STATUS_OVERRUN 0x1000 /* already 8 packets in RX FIFO */
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#define FD_RX_UNDERRUN 0x2000 /* host read past end of packet */
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#define FD_RX_RECEIVING 0x8000 /* packet being received now */
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/* media type and status bits */
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#define MT_S_SQE_ENABLE 0x0008 /* enable SQE error detection */
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#define MT_S_COLLISION 0x0010 /* (?) collision in progress */
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#define MT_S_CARRIER 0x0020 /* (?) carrier sensed currently */
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#define MT_S_JABBER_ENABLE 0x0040 /* enable jabber and polarity detect */
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#define MT_S_LINK_BEAT_ENABLE 0x0080 /* enable TPE link beat */
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#define MT_S_UNSQUELCH 0x0100 /* unsquelch status */
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#define MT_S_JABBER 0x0200 /* jabber status */
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#define MT_S_POLARITY 0x0400 /* polarity swap status */
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#define MT_S_LINK_BEAT 0x0800 /* link beat correct status */
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#define MT_S_SQE 0x1000 /* SQE present status */
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#define MT_S_INTERNAL_ENDEC 0x2000 /* internal encoder/decoder in use */
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#define MT_S_BNC 0x4000 /* BNC transceiver in use */
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#define MT_S_AUI_DISABLE 0x8000 /* AUI interface disabled */
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/* command opcodes (uppper 5 bits of command register) */
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#define GLOBAL_RESET 0x0000 /* global reset (powerup equiv.) */
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#define SELECT_WINDOW 0x0800 /* select register window */
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#define START_COAX 0x1000 /* start coaxial transciever */
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#define RX_DISABLE 0x1800 /* disable ethernet receiver */
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#define RX_ENABLE 0x2000 /* enable ethernet receiver */
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#define RX_RESET 0x2800 /* reset ethernet receiver */
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#define RX_DISCARD 0x4000 /* discard remainder of top FIFO pkt */
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#define TX_ENABLE 0x4800 /* enable ethernet transmitter */
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#define TX_DISABLE 0x5000 /* disable ethernet transmitter */
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#define TX_RESET 0x5800 /* reset ethernet transmitter */
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#define REQ_INTERRUPT 0x6000 /* set interrupt requested bit */
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#define ACK_INTERRUPT 0x6800 /* acknowledge interrupt conditions */
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#define MASK_INTERRUPT 0x7000 /* set interrupt mask bits */
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#define MASK_STATUS 0x7800 /* set status mask bits */
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/* the "read zero mask" */
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#define SET_RX_FILTER 0x8000 /* set receive filter bits */
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#define SET_RX_THRESH 0x8800 /* set receive early threshold */
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#define SET_TX_AVAIL 0x9000 /* set transmit available threshold */
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#define SET_TX_START 0x9800 /* set transmit start threshold */
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#define STATS_ENABLE 0xa800 /* enable statistics collection */
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#define STATS_DISABLE 0xb000 /* disable statistics collection */
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#define STOP_COAX 0xb800 /* stop coaxial transciever */
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#define SET_TX_RECLAIM 0xc000 /* (MCA) set tx reclaim threshold */
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/* receive filter command argument bits */
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#define RX_F_STATION_IA 0x01 /* accept individual address */
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#define RX_F_MULTICAST 0x02 /* accept multicast (group) addresses */
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#define RX_F_BROADCAST 0x04 /* accept broadcast address */
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#define RX_F_PROMISCUOUS 0x08 /* accept all addresses */
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#define RX_F_NORMAL (RX_F_STATION_IA | RX_F_BROADCAST)
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/* board status bits (also acknowledge and mask bits) */
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#define INTERRUPT_LATCH 0x0001 /* raise interrupt to host */
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#define ADAPTER_FAILURE 0x0002 /* error unrecoverable by adapter */
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/* tx overrun, rx underrun, or */
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/* hypothetical hardware errors */
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#define TX_COMPLETE 0x0004 /* tx finished with error or */
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/* packet interrupt bit was set */
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#define TX_AVAILABLE 0x0008 /* tx available threshold exceeded */
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#define RX_COMPLETE 0x0010 /* a complete packet is available */
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#define RX_EARLY 0x0020 /* rx early threshold exceeded */
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#define INTERRUPT_REQ 0x0040 /* set by request interrupt command */
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#define UPDATE_STATS 0x0080 /* one or more statistics counters */
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/* needs to be flushed */
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#define STATUS_MASK 0x00ff /* pick status bits out of register */
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#define COMMAND_IN_PROGRESS 0x1000 /* last command still being processed */
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#define WINDOW_MASK 0xe000 /* current register window selection */
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/* transmit status register bits */
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#define TX_S_RECLAIM 0x02 /* tx reclaim (MCA only) */
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#define TX_S_OVERFLOW 0x04 /* tx status overflow (lost info) */
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#define TX_S_MAX_COLL 0x08 /* maximum collisions reached */
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#define TX_S_UNDERRUN 0x10 /* underrun, tx reset required */
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#define TX_S_JABBER 0x20 /* jabber error, tx reset required */
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#define TX_S_INTERRUPT 0x40 /* interrupt on successful xmit */
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#define TX_S_COMPLETE 0x80 /* transmission complete */
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/* This bit denotes a valid status */
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/* when set; valid status is popped */
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/* off the stack by a write cycle to */
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/* the transmit status register */
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/* transmit free bytes constants */
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#define TX_IDLE_COUNT 0x7f8 /* 2,040; supposed to be 2,044 */
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/* use a >= test to see if tx idle */
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/* receive status register bits */
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#define RX_S_CNT_MASK 0x07ff /* received byte count field */
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#define RX_S_CODE_MASK 0x3800 /* error code field */
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#define RX_S_OVERRUN 0x0000 /* overrun error */
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#define RX_S_RUNT 0x1800 /* runt packet error */
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#define RX_S_ALIGN 0x2000 /* alignment (framing) error */
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#define RX_S_CRC 0x2800 /* CRC error */
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#define RX_S_OVERSIZE 0x0800 /* oversize packet error (>1514) */
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#define RX_S_DRIBBLE 0x1000 /* dribble bit(s); this code is */
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/* valid when error bit is not set */
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#define RX_S_ERROR 0x4000 /* error in rx packet, code above */
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#define RX_S_INCOMPLETE 0x8000 /* packet is incomplete or FIFO empty */
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/* opposite of transmit status! */
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/* transmit packet preamble bits and fields */
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#define TX_F_LEN_MASK 0x07ff /* length field */
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#define TX_F_INTERRUPT 0x8000 /* interrupt on transmit complete */
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#define TX_F_DWORD_MASK 0xfffc /* mask to round lengths to dword */
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#define TX_F_PREAMBLE_SIZE 4 /* size of packet length "preamble" */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCelt3c509Endh */
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