241 lines
7.1 KiB
C
241 lines
7.1 KiB
C
/* smpSimsolarisP.h - simsolaris private SMP assembler definitions hdr file */
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/*
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* Copyright (c) 2006-2011 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use of this
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* software may be licensed only pursuant to the terms of an applicable
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* Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01s,24feb11,elp added vxsimHostCpuDelay() vxsimHostCpuWakeup()
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CQ:WIND00151275.
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01r,29jul10,pad Moved extern C statement after include statements.
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01q,15may09,gls moved VX_INSTR_BARRIER() to vxAtomicArchLibCommon.h
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01p,26sep08,gls added _WRS_KERNEL_LOCK_VAR_ALIGN
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01o,27aug08,jpb Renamed VSB header file
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01n,24jun08,jpb Added include path for kernel configurations options set in
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vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
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01m,20jun08,zl replaced _WRS_ASM() with _WRS_BARRIER()
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01l,18jan08,gls added VX_INSTR_BARRIER()
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01k,23jul07,elp include vxsimHostLibP.h to remove extern vxsimHostSleep().
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01j,19jul07,rlp Declared vxsimHostSleep() as extern, this is a temporary fix
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to be able to build the aim directory.
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01i,16jul07,elp added _WRS_ARCH_CPU_DELAY() macro.
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01h,17apr07,kk move VX_MAX_SMP_CPUS to archSolaris.h
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01g,16mar07,elp fixed cplus build
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01f,08mar07,dbt Removed inclusion of mmuArchLib.h
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01e,19dec06,elp moved simStatus and simPendingIntLvl to host,
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added macros to get WIND_VARS locked, added intNest.
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01d,11dec06,kk removed references to VX_KERNEL_VARS define, no longer needed
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01c,30nov06,dbt Increased maximum number of CPUs to 32.
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01b,24nov06,dbt Added missing macros.
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01a,07sep06,elp created
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*/
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#ifndef __INCsmpSimsolarisPh
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#define __INCsmpSimsolarisPh
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/*
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* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
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* Any compilation using definitions from this file will not *
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* be binary-compatible between the UP and SMP environments. *
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* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
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*/
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#include <vsbConfig.h>
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#ifdef _WRS_CONFIG_SMP
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/*
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* Much like the _WRS_WIND_VARS_ALIGN the _WRS_KERNEL_LOCK_VAR_ALIGN macro
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* must be defined for the common CPU build variants (e.g. PPC32, MIPS32,
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* XSCALE, etc), representing the maximum cache line size of the variants of
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* the respective arch.
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*
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* For the SIMSPARCSOLARIS this is 128 bytes.
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*/
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#define _WRS_KERNEL_LOCK_VAR_ALIGN 128
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#ifndef _ASMLANGUAGE
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#include <private/vxsimHostLibP.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define _WRS_ARCH_CPU_DELAY() (vxsimHostCpuDelay (0))
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#define _WRS_ARCH_CPU_DELAY_MS(ms) (vxsimHostCpuDelay (ms))
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#define _WRS_ARCH_CPU_WAKEUP(cpuIx) (vxsimHostCpuWakeup (cpuIx))
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extern UINT32 * pVxCpuIndex;
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/* optimized access without function call */
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#define _WRS_CPU_INDEX_GET() (*pVxCpuIndex)
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#ifdef __cplusplus
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}
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#endif
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#endif /* ASMLANGUAGE */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* This macro defines the alignment requirement for the WIND_VARS structure.
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*
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* There are 3 factors involved in selection of this value.
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*
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* 1. It's definition is no LESS than the maximum value of
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* _CPU_CACHE_ALIGN_SIZE, and may be larger to provide for future
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* cache line length growth.
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* 2. It must be at least as large as the WIND_VARS structure.
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* 3. It must be a power of 2.
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*
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* For example:
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* If WIND_VARS is 56 bytes, _WRS_WIND_VARS_ALIGN must be no less than 64
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* (rule 1).
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* if WIND_VARS is 72 bytes, _WRS_WIND_VARS_ALIGN must be no less than 128
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* (rules 2 and 3).
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*/
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#define _WRS_WIND_VARS_ALIGN 128
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#define _WRS_WIND_VARS_ALIGN_SHIFT 7
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#ifndef _ASMLANGUAGE
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typedef struct wind_vars_arch
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{
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UINT32 cpu_intNest; /* 0x0: interrupt nested count */
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struct mmuTransTblStruct * cpu_pMmuCurrentTransTbl;
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/* 0x04: current MMU trans table */
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UINT32 cpu_ctxLoadIntLock; /* 0x8: context load intlock */
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} WIND_VARS_ARCH;
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#define _WRS_WIND_VARS_ARCH WIND_VARS_ARCH cpu_archVars
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/* macros to access the arch-specific fields of the vxKernelVars struct */
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#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
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_WRS_KERNEL_GLOBAL_ACCESS (archVars.cpu_##glob)
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#define _WRS_WIND_VARS_ARCH_SET(cpuid,glob,var) \
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_WRS_KERNEL_CPU_GLOBAL_SET(cpuid,archVars.cpu_##glob,var)
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#define _WRS_WIND_VARS_ARCH_LOCKED_GET(glob, var) \
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_WRS_KERNEL_LOCKED_GLOBAL_GET (archVars.cpu_##glob, var)
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#else /* _ASMLANGUAGE */
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#define _WRS_WIND_VARS_OFFSET_intNest \
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(_WRS_WIND_VARS_OFFSET_archVars+0x0)
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#define _WRS_WIND_VARS_OFFSET_pMmuCurrentTransTbl \
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(_WRS_WIND_VARS_OFFSET_archVars+0x4)
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#define _WRS_WIND_VARS_OFFSET_ctxLoadIntLock \
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(_WRS_WIND_VARS_OFFSET_archVars+0x8)
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#define _WRS_SIMSPARC_VAR_ADRS(label) FUNC(vxKernelVars+OFFSET_##label)
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#define _WRS_WIND_VARS_OFFSET(reg) sll reg,_WRS_WIND_VARS_ALIGN_SHIFT,reg;
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/*
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* take the value at *pVxCpuIndex and shift to get the vxKernelVar index
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* 0,128,256 ...
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*/
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#define _SIMSPARC_CPU_INDEX_GET(reg,scratch) \
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sethi %hi(FUNC(pVxCpuIndex)),reg; \
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ld [reg + %lo(FUNC(pVxCpuIndex))],reg; \
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ld [reg], reg; \
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_WRS_WIND_VARS_OFFSET(reg)
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#define _WRS_LOAD_REG_WITH_VAR_BASE(label,reg) \
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set FUNC(vxKernelVars),reg; \
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add reg,_WRS_WIND_VARS_OFFSET_##label,reg;
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#define _SIMSPARC_PER_CPU_ADRS_GET(reg,scratch,label) \
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_SIMSPARC_CPU_INDEX_GET(reg,scratch) \
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
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add reg,scratch,reg;
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#define _SIMSPARC_PER_CPU_VALUE_GET(reg,scratch,label) \
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_SIMSPARC_CPU_INDEX_GET(reg,scratch) \
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
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ld [reg + scratch], reg;
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#define _SIMSPARC_PER_CPU_VALUE_CLEAR(reg,scratch,label)\
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_SIMSPARC_CPU_INDEX_GET(reg,scratch) \
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
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st %g0, [reg + scratch];
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#define _SIMSPARC_PER_CPU_VALUE_INC(reg,scratch,label) \
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_SIMSPARC_CPU_INDEX_GET(reg,scratch) \
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
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add scratch,reg,scratch; \
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ld [scratch], reg; \
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add reg,1,reg; \
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st reg,[scratch]
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#else /* _WRS_CONFIG_SMP */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define _WRS_CPU_INDEX_GET() 0
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/* macro to access the arch-specific fields */
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#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
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_WRS_KERNEL_GLOBAL_ACCESS (glob)
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#define _WRS_WIND_VARS_ARCH_SET(ignored,glob,var) \
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_WRS_KERNEL_CPU_GLOBAL_SET(ignored,glob,var)
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#define _WRS_WIND_VARS_ARCH_LOCKED_GET(glob,var) \
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_WRS_KERNEL_LOCKED_GLOBAL_GET (glob,var)
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#ifdef _ASMLANGUAGE
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#define _SIMSPARC_PER_CPU_ADRS_GET(reg,scratch,label) \
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set FUNC(label),reg;
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#define _SIMSPARC_PER_CPU_VALUE_GET(reg,scratch,label) \
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sethi %hi(FUNC(label)),reg; \
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ld [reg + %lo(FUNC(label))],reg;
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#define _SIMSPARC_PER_CPU_VALUE_CLEAR(reg,scratch,label)\
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sethi %hi(FUNC(label)),reg; \
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st %g0, [reg + %lo(FUNC(label))]
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#define _SIMSPARC_PER_CPU_VALUE_INC(reg,scratch,label) \
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sethi %hi(FUNC(label)),reg; \
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ld [reg + %lo(FUNC(label))],reg; \
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add reg, 1, reg; \
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sethi %hi(FUNC(label)),scratch; \
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st reg, [scratch + %lo(FUNC(label))]
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _WRS_CONFIG_SMP */
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#endif /* __INCsmpSimsolarisPh */
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