70 lines
1.7 KiB
C
70 lines
1.7 KiB
C
/* dsmMipP.h - private assembler definitions header file for disassembler */
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/*
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* Copyright (c) 2010 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01a,28apr10,rlg written.
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*/
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#ifndef __INCdsmMipsPh
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#define __INCdsmMipsPh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <vsbConfig.h>
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#include <arch/mips/archMips.h>
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#include <arch/mips/regsMips.h>
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#include <arch/mips/mipsExcPage.h>
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#include <private/kernelLockLibP.h>
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#ifdef _ASMLANGUAGE
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#include <private/windLibP.h>
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#endif /* _ASMLANGUAGE */
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/*
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The CPU bits defined below can be used to identify instructions which
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are only valid on a particular set of CPU types. At some point in the
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future it might be valuable to add bits which identify CPU groups such
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as ISA, ISA2, etc. If you add any entry to this list, a corresponding
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entry needs to be made to the CPUMASK, defined in /target/src/arch/mips
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dsmLib.c.
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*/
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#define dsmANY (0)
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#define dsmMIPS1 (1 << 0)
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#define dsmMIPS2 (1 << 1) /* MIPSI2 */
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#define dsmMIPS3 (1 << 2) /* MIPSI3 */
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#define dsmMIPS4 (1 << 3)
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#define dsmMIPS32 (1 << 4) /* MIPSI32 */
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#define dsmMIPS64 (1 << 5) /* MIPSI64 */
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#define dsmMIPS32R2 (1 << 6) /* MIPSI32R2 */
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#define dsmMIPS64R2 (1 << 7) /* MIPSI64R2 */
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#define dsmCW4011 (1 << 8)
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#define dsmR4650 (1 << 9)
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#define dsmVR5400 (1 << 10)
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#define dsmRMI_XLX (1 << 11)
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#define dsmOCTEON (1 << 12)
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#define dsmOCTEONII (1 << 13)
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#define dsmUNKNOWN (1 << 31)
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UINT dsmMipsSupportISAs (void );
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCdsmMipsPh */
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