121 lines
3.2 KiB
C
121 lines
3.2 KiB
C
/* regsP7.h - Pentium4 architecture specific registers */
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/* Copyright 2002 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01a,02sep02,hdn written
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*/
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#ifndef __INCregsP7h
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#define __INCregsP7h
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* MSR, Pentium4 specific */
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#define MSR_EBC_HARD_POWERON 0x002a
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#define MSR_EBC_SOFT_POWERON 0x002b
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#define MSR_EBC_FREQUENCY_ID 0x002c
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#define MSR_LER_FROM_LIP 0x01d7
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#define MSR_LER_TO_LIP 0x01d8
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#define MSR_LASTBRANCH_TOS 0x01da
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#define MSR_LASTBRANCH_0 0x01db
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#define MSR_LASTBRANCH_1 0x01dc
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#define MSR_LASTBRANCH_2 0x01dd
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#define MSR_LASTBRANCH_3 0x01de
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#define MSR_BPU_COUNTER0 0x0300
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#define MSR_BPU_COUNTER1 0x0301
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#define MSR_BPU_COUNTER2 0x0302
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#define MSR_BPU_COUNTER3 0x0303
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#define MSR_MS_COUNTER0 0x0304
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#define MSR_MS_COUNTER1 0x0305
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#define MSR_MS_COUNTER2 0x0306
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#define MSR_MS_COUNTER3 0x0307
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#define MSR_FLAME_COUNTER0 0x0308
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#define MSR_FLAME_COUNTER1 0x0309
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#define MSR_FLAME_COUNTER2 0x030a
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#define MSR_FLAME_COUNTER3 0x030b
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#define MSR_IQ_COUNTER0 0x030c
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#define MSR_IQ_COUNTER1 0x030d
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#define MSR_IQ_COUNTER2 0x030e
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#define MSR_IQ_COUNTER3 0x030f
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#define MSR_IQ_COUNTER4 0x0310
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#define MSR_IQ_COUNTER5 0x0311
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#define MSR_BPU_CCCR0 0x0360
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#define MSR_BPU_CCCR1 0x0361
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#define MSR_BPU_CCCR2 0x0362
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#define MSR_BPU_CCCR3 0x0363
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#define MSR_MS_CCCR0 0x0364
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#define MSR_MS_CCCR1 0x0365
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#define MSR_MS_CCCR2 0x0366
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#define MSR_MS_CCCR3 0x0367
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#define MSR_FLAME_CCCR0 0x0368
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#define MSR_FLAME_CCCR1 0x0369
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#define MSR_FLAME_CCCR2 0x036a
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#define MSR_FLAME_CCCR3 0x036b
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#define MSR_IQ_CCCR0 0x036c
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#define MSR_IQ_CCCR1 0x036d
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#define MSR_IQ_CCCR2 0x036e
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#define MSR_IQ_CCCR3 0x036f
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#define MSR_IQ_CCCR4 0x0370
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#define MSR_IQ_CCCR5 0x0371
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#define MSR_BSU_ESCR0 0x03a0
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#define MSR_BSU_ESCR1 0x03a1
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#define MSR_FSB_ESCR0 0x03a2
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#define MSR_FSB_ESCR1 0x03a3
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#define MSR_FIRM_ESCR0 0x03a4
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#define MSR_FIRM_ESCR1 0x03a5
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#define MSR_FLAME_ESCR0 0x03a6
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#define MSR_FLAME_ESCR1 0x03a7
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#define MSR_DAC_ESCR0 0x03a8
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#define MSR_DAC_ESCR1 0x03a9
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#define MSR_MOB_ESCR0 0x03aa
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#define MSR_MOB_ESCR1 0x03ab
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#define MSR_PMH_ESCR0 0x03ac
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#define MSR_PMH_ESCR1 0x03ad
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#define MSR_SAAT_ESCR0 0x03ae
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#define MSR_SAAT_ESCR1 0x03af
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#define MSR_U2L_ESCR0 0x03b0
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#define MSR_U2L_ESCR1 0x03b1
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#define MSR_BPU_ESCR0 0x03b2
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#define MSR_BPU_ESCR1 0x03b3
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#define MSR_IS_ESCR0 0x03b4
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#define MSR_IS_ESCR1 0x03b5
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#define MSR_ITLB_ESCR0 0x03b6
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#define MSR_ITLB_ESCR1 0x03b7
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#define MSR_CRU_ESCR0 0x03b8
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#define MSR_CRU_ESCR1 0x03b9
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#define MSR_IQ_ESCR0 0x03ba
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#define MSR_IQ_ESCR1 0x03bb
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#define MSR_RAT_ESCR0 0x03bc
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#define MSR_RAT_ESCR1 0x03bd
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#define MSR_SSU_ESCR0 0x03be
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#define MSR_MS_ESCR0 0x03c0
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#define MSR_MS_ESCR1 0x03c1
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#define MSR_TBPU_ESCR0 0x03c2
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#define MSR_TBPU_ESCR1 0x03c3
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#define MSR_TC_ESCR0 0x03c4
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#define MSR_TC_ESCR1 0x03c5
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#define MSR_IX_ESCR0 0x03c8
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#define MSR_IX_ESCR1 0x03c9
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#define MSR_ALF_ESCR0 0x03ca
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#define MSR_ALF_ESCR1 0x03cb
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#define MSR_CRU_ESCR2 0x03cc
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#define MSR_CRU_ESCR3 0x03cd
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#define MSR_CRU_ESCR4 0x03e0
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#define MSR_CRU_ESCR5 0x03e1
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#define MSR_TC_PRECISE_EVENT 0x03f0
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#define MSR_PEBS_MATRIX_VERT 0x03f2
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCregsP7h */
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