223 lines
6.3 KiB
C
223 lines
6.3 KiB
C
/* mmuPro32Lib.h - mmuPpro32Lib header for i86. */
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/*
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* Copyright (c) 1984-2003, 2009, 2011, 2014, 2018 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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modification history
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--------------------
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01k,18jul18,hbu kernel page table isolation support (F10571)
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01j,02may14,jb VXW6-81787 - add Intel Write Combining Option
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01i,19jan11,jb Fix for WIND00185635 - mmu deoptimize locks do not work
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01h,08sep09,rbc WIND00177961 - vmStateSet() can no longer been called from an
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ISR
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01g,21apr09,rbc Page Table Optimization.
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01f,09dec03,zmm Ported to Base6 from AE version of mmuPro32Lib.h 01f,30nov99
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01e,12jun02,hdn added arch specific VM library APIs' prototype
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01d,23may02,hdn replaced PAGE_SIZE with PD_SIZE and PT_SIZE
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01c,22aug01,hdn moved GDT and GDT_ENTRIES to regsI86.h
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01b,13may98,hdn added _ASMLANGUAGE macro.
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01a,11apr97,hdn written.
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*/
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#ifndef __INCmmuPro32Libh
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#define __INCmmuPro32Libh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define PAGE_SIZE 0x1000
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#define PAGE_BLOCK_SIZE 0x400000
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#define PAGE_SIZE_4KB 0x1000
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#define PAGE_SIZE_4MB 0x400000
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#ifdef _WRS_CONFIG_KPTI
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#define PD_TBL_SIZE (2 * PAGE_SIZE_4KB)
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#define MMU_UMTBL_OFFSET (PAGE_SIZE_4KB)
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#else
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#define PD_TBL_SIZE PAGE_SIZE_4KB
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#endif
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#define N_PTES 1024
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#define N_PDES 1024
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#define DIRECTORY_BITS 0xffc00000
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#define TABLE_BITS 0x003ff000
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#define OFFSET_BITS_4KB 0x00000fff
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#define OFFSET_BITS_4MB 0x003fffff
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#define DIRECTORY_INDEX 22
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#define TABLE_INDEX 12
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#define PTE_TO_ADDR_4KB 0xfffff000
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#define PTE_TO_ADDR_4MB 0xffc00000
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#define PTE_INVALID PTE_TO_ADDR_4KB
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#define PDE_INVALID PTE_TO_ADDR_4MB
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#define PAGES_PER_BLOCK 0x400
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#define ADDR_TO_PAGE 12
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#define ADDR_TO_PAGEBASE 22
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#ifndef _ASMLANGUAGE
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#define PAGE_TABLE_PRESENT 1
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#define PAGE_TABLE_RW 1
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#define PAGE_TABLE_US 1
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#define PAGE_TABLE_PWT 1
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#define PAGE_TABLE_PCD 1
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#define PAGE_TABLE_ACCESS 1
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#define PAGE_TABLE_DIRTY 1
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#define PAGE_TABLE_4KB 0
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#define PAGE_TABLE_4MB 1
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#define PAGE_TABLE_GLOBAL 1
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/* Define use of hardware available bits */
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#define PAGE_TABLE_AVAIL_MASK 0x7
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#define PAGE_TABLE_MASK_NO_BLOCK 0x1
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#define PAGE_TABLE_NO_BLOCK 0x1
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typedef struct
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{
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unsigned present:1;
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unsigned rw:1;
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unsigned us:1;
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unsigned pwt:1;
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unsigned pcd:1;
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unsigned access:1;
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unsigned dirty:1;
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unsigned pagesize:1;
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unsigned global:1;
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unsigned avail:3;
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unsigned page:20;
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} PTE_FIELD;
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typedef union pte
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{
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PTE_FIELD field;
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unsigned int bits;
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} PTE;
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typedef struct mmuTransTblStruct
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{
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PTE *pDirectoryTable;
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PTE *pAltDirectoryTable;
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VX_SEMAPHORE(mmuTransTblSem);
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} MMU_TRANS_TBL;
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#if (_VX_CPU != _VX_PENTIUM)
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typedef union mmuPatReg
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{
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UINT64 mmuFullPat;
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UINT32 mmuHalfPat[2];
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UCHAR mmuCharPat[8];
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} MMU_PAT_REG;
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#define IA32_PAT_MSR 0x277
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#define IA32_PAT_WC_IDX 0x02
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#define IA32_PAT_WC 0x01
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#endif /* (_VX_CPU != _VX_PENTIUM) */
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#define MMU_STATE_MASK_VALID 0x001
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#define MMU_STATE_MASK_WRITABLE 0x002
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#define MMU_STATE_MASK_USER 0x004
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#define MMU_STATE_MASK_PROTECTION 0x006
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#define MMU_STATE_MASK_WRITETHROUGH 0x008
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#define MMU_STATE_MASK_WBACK 0x008
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#define MMU_STATE_MASK_CACHEABLE 0x018 /* 0x018 was 0x10 in AE version */
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#define MMU_STATE_MASK_GLOBAL 0x100
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#define MMU_STATE_MASK_NO_BLOCK 0x200
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#ifdef _WRS_CONFIG_KPTI
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#define MMU_STATE_MASK_UMPT 0x800
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#define MMU_STATE_MASK_STATE 0xb1f
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#else
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#define MMU_STATE_MASK_STATE 0x31f
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#endif
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#define MMU_STATE_VALID 0x001
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#define MMU_STATE_VALID_NOT 0x000
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#define MMU_STATE_WRITABLE 0x002
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#define MMU_STATE_WRITABLE_NOT 0x000
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#define MMU_STATE_USER 0x004
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#define MMU_STATE_USER_NOT 0x000
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#define MMU_STATE_WRITETHROUGH 0x008
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#define MMU_STATE_WBACK 0x000
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#define MMU_STATE_COPYBACK 0x000
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#define MMU_STATE_CACHEABLE_NOT 0x018 /* 0x18 was 0x10 in AE version */
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#define MMU_STATE_WBACK_NOT MMU_STATE_CACHEABLE_NOT
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#if (_VX_CPU != _VX_PENTIUM)
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#define MMU_STATE_MASK_WCOMBINE MMU_STATE_MASK_CACHEABLE
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#define MMU_STATE_WCOMBINE 0x010 /* This requires mod to default PAT Table */
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#define MMU_STATE_WCOMBINE_NOT 0x000
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#endif /* (_VX_CPU != _VX_PENTIUM) */
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#define MMU_STATE_CACHEABLE 0x000
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#define MMU_STATE_GLOBAL 0x100
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#define MMU_STATE_GLOBAL_NOT 0x000
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#define MMU_STATE_NO_BLOCK 0x200
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#define MMU_STATE_NO_BLOCK_NOT 0x000
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#ifdef _WRS_CONFIG_KPTI
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#define MMU_STATE_UMPT 0x800
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#define MMU_STATE_UMPT_NOT 0x000
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#endif
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#define MMU_STATE_SUP_RO (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE_NOT) /* 0x0 */
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#define MMU_STATE_USR_RO (MMU_STATE_USER | MMU_STATE_WRITABLE_NOT) /* 0x4 */
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#define MMU_STATE_SUP_RW (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE) /* 0x2 */
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#define MMU_STATE_USR_RW (MMU_STATE_USER | MMU_STATE_WRITABLE) /* 0x6 */
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/* wpOff is used to temporarily override supervisor write-protection.
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* When using wpOff, interrupts should
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* be locked because this disables write-protection system wide!
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* Before unlocking interrupts, be sure to do a wpOn().
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*/
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#define wpOff() vxCr0Set (vxCr0Get() & 0xfffeffff)
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#define wpOn() vxCr0Set (vxCr0Get() | 0x00010000)
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/* function declarations */
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#if defined(__STDC__) || defined(__cplusplus)
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extern STATUS mmuPro32LibInit (int pageSize);
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extern STATUS mmuPro32Enable (BOOL enable);
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extern void mmuPro32On ();
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extern void mmuPro32Off ();
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extern void mmuPro32TLBFlush ();
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extern void mmuPro32PdbrSet (MMU_TRANS_TBL *transTbl);
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extern void mmuPro32Show (MMU_TRANS_TBL *transTbl, void * vaddr);
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extern MMU_TRANS_TBL *mmuPro32PdbrGet ();
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#else /* __STDC__ */
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extern STATUS mmuPro32LibInit ();
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extern STATUS mmuPro32Enable ();
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extern void mmuPro32On ();
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extern void mmuPro32Off ();
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extern void mmuPro32TLBFlush ();
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extern void mmuPro32PdbrSet ();
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extern void mmuPro32Show ();
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extern MMU_TRANS_TBL *mmuPro32PdbrGet ();
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#endif /* __STDC__ */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCmmuPro32Libh */
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