251 lines
8.4 KiB
C
251 lines
8.4 KiB
C
/* ctB69000Vga.c - a CHIPS B69000 initialization source module */
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/* Copyright 1984-2000 Wind River Systems, Inc. */
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#include "copyright_wrs.h"
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/*
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modification history
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--------------------
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01a,26mar00,ms written.
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*/
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/*
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DESCRIPTION
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The 69000 is the first product in the CHIPS family of portable graphics
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accelerator product line that integrates high performance memory technology
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for the graphics frame buffer. Based on the proven HiQVideo graphics
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accelerator core, the 69000 combines state-of-the-art flat panel controller
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capabilities with low power, high performance integrated memory. The result
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is the start of a high performance, low power, highly integrated solution for
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the premier family of portable graphics products.
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.IP "High Performance Integrated Memory"
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The 69000 is the first member of the HiQVideo family to provide integrated high
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performance synchronous DRAM (SDRAM) memory technology. Targeted at the
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mainstream notebook market, the 69000 incorporates 2MB of proprietary integrated
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SDRAM for the graphics/video frame buffer. The integrated SDRAM memory can
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support up to 83MHz operation, thus increasing the available memory bandwidth
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for the graphics subsystem. The result is support for additional high color /
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high resolution graphics modes combined with real-time video acceleration. This
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additional bandwidth also allows more flexibility in the other graphics
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functions intensely used in Graphical User Interfaces (GUIs) such as Microsoft
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Windows.
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.IP "Frame-Based AGP Compatibility"
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The 69000 graphics is designed to be used with either 33MHz PCI, or with AGP as a
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frame-based AGP device, allowing it to be used with the AGP interface provided by
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the latest core logic chipsets.
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.IP "HiQColor TM Technology"
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The 69000 integrates CHIPS breakthrough HiQColor technology. Based on the CHIPS
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proprietary TMED (Temporal Modulated Energy Distribution) algorithm, HiQColor
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technology is a unique process that allows the display of 16.7 million true
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colors on STN panels without using Frame Rate Control (FRC) or dithering. In
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addition, TMED also reduces the need for the panel tuning associated with
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current FRC-based algorithms. Independent of panel response, the TMED algorithm
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eliminates all of the flaws (such as shimmer, Mach banding, and other motion
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artifacts) normally associated with dithering and FRC. Combined with the new
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fast response, high-contrast, and low-crosstalk technology found in new STN
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panels, HiQColor technology enables the best display quality and color fidelity
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previously only available with TFT technology.
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.IP "Versatile Panel Support"
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The HiQVideo family supports a wide variety of monochrome and color Single-
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Panel, Single-Drive (SS) and Dual-Panel, Dual Drive (DD), standard and high-
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resolution, passive STN and active matrix TFT/MIM LCD, and EL panels. With
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HiQColor technology, up to 256 gray scales are supported on passive STN LCDs. Up
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to 16.7M different colors can be displayed on passive STN LCDs and up to 16.7M
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colors on 24- bit active matrix LCDs.
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The 69000 offers a variety of programmable features to optimize display quality.
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Vertical centering and stretching are provided for handling modes with less than
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480 lines on 480-line panels. Horizontal and vertical stretching capabilities
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are also available for both text and graphics modes for optimal display of VGA
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text and graphics modes on 800x600, 1024x768 and 1280x1024 panels.
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.IP "Television NTSC/PAL Flicker Free Output"
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The 69000 uses a flicker reduction process which makes text of all fonts and
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sizes readable by reducing the flicker and jumping lines on the display.
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.IP "HiQVideo T Multimedia Support"
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The 69000 uses independent multimedia capture and display systems on-chip.
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The capture system places data in display memory (usually off screen) and
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the display system places the data in a window on the screen.
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.IP "Low Power Consumption"
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The 69000 uses a variety of advanced power management features to reduce power
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consumption of the display sub-system and to extend battery life. Optimized for
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3.3V operation, the 69000 internal logic, bus and panel interfaces operate at
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3.3V but can tolerate 5V operation.
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.IP "Software Compatibility / Flexibility"
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The HiQVideo controllers are fully compatible with the VGA standard at both the
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register and BIOS levels. CHIPS and third-party vendors supply a fully VGA
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compatible BIOS, end-user utilities and drivers for common application programs.
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.IP "Acceleration for All Panels and All Modes"
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The 69000 graphics engine is designed to support high performance graphics and
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video acceleration for all supported display resolutions, display types, and
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color modes. There is no compromise in performance operating in 8, 16, or 24 bpp
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color modes allowing true acceleration while displaying up to 16.7M colors.
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.LP
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.I USAGE
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This library provides initialization routines to configure CHIPS B69000 (VGA)
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in alphanumeric mode.
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The functions addressed here include:
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.IP " -"
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Initialization of CHIPS B69000 IC.
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.LP
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.I USER INTERFACE
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.CS
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STATUS ctB69000VgaInit
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(
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VOID
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)
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.CE
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This routine will initialize the VGA card if present in PCI connector,
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sets up register set in VGA 3+ mode and loads the font in plane 2.
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INCLUDE FILES: NONE.
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*/
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/* includes */
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#include "vxWorks.h"
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#include "sysLib.h"
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#include "drv/pci/pciConfigLib.h"
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#include "vgaInit.c"
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/* defines */
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#define CTB69000VGA_VENID 0x102C
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#define CTB69000VGA_DEVID 0x00C0
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#define CTB69000VGA_XR_PORT 0x3D6 /* Extended Register Index Port */
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#define CTB69000VGA_XR_DATA_PORT 0x3D7 /* Extended Register Data Port */
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#define CTB69000VGA_FR_PORT 0x3D0 /* Flat Panel Index Port */
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#define CTB69000VGA_FR_DATA_PORT 0x3D1 /* Flat Panel Data Port */
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#define CTB69000VGA_MR_PORT 0x3D2 /* Multimedia Index Port */
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/*******************************************************************************
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*
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* ctB69000VgaInit - initializes the B69000 chip and loads font in memory.
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*
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* This routine will initialize the VGA card if present in PCI connector,
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* sets up register set in VGA 3+ mode and loads the font in plane 2.
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*
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* RETURNS: OK/ERROR
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*/
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STATUS ctB69000VgaInit
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(
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void
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)
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{
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int pciBus = 0;
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int pciDevice = 0;
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int pciFunc = 0;
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/* check PCI BASED - CHIPS B69000's presence on the bus */
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if (pciFindDevice (CTB69000VGA_VENID, CTB69000VGA_DEVID, 0,
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&pciBus, &pciDevice, &pciFunc) != OK)
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{
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return ERROR;
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}
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/* enable mapped memory and IO addresses */
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pciConfigOutLong (pciBus, pciDevice, pciFunc, 0x04, 0x7);
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/*
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* Intialize CHIPS B69000 specific registers.
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*/
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/* Extension Registers */
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vgaRegSet (CTB69000VGA_XR_PORT, 0x0005);
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vgaRegSet (CTB69000VGA_XR_PORT, 0xC006);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x0308);
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/* [0] = Paged; [1] = Linear Mapping; */
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vgaRegSet (CTB69000VGA_XR_PORT, 0x000A);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x010B);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x000E);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x0040);
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vgaRegSet (CTB69000VGA_XR_PORT, 0xBC63);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x0080);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x0081);
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/* Fout for DCLK0 = 25 Mhz */
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vgaRegSet (CTB69000VGA_XR_PORT, 0xD1C0);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x1CC1);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x00C2);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x24C3);
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/* Fout for DCLK1 = 28 Mhz */
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vgaRegSet (CTB69000VGA_XR_PORT, 0x55C4);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x09C5);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x00C6);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x24C7);
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/* Fout for DCLK2 = Mhz */
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vgaRegSet (CTB69000VGA_XR_PORT, 0x6BC8);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x3CC9);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x00CA);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x21CB);
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/* Fout for MCLK = 83 Mhz */
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vgaRegSet (CTB69000VGA_XR_PORT, 0x10CE);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x38CC);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x03CD);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x90CE);
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/* Enable MCLK and DCLK synthesizers */
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vgaRegSet (CTB69000VGA_XR_PORT, 0x06CF);
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/* Enable DAC, Palette, DCLK-Vco and MCLK-Vco */
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vgaRegSet (CTB69000VGA_XR_PORT, 0x0FD0);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x01D1);
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/* Flat Panel Registers */
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vgaRegSet (CTB69000VGA_FR_PORT, 0x0101);
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/*
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* Intialize VGA compatible register set on B69000,
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* and download font in memory for alphanumeric mode.
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*/
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vgaInit ();
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return OK;
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}
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