149 lines
4.5 KiB
C
149 lines
4.5 KiB
C
/* vxbKinetisGpio.h - interrupt controller for freescale Kinetis */
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/*
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* Copyright (c) 2013 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01a,17aug13,yjw created
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*/
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#ifndef __INCvxbKinetisGpioh
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#define __INCvxbKinetisGpioh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define BITBAND_ALIAS_ADDRESS(addr, bit) \
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((((UINT32)(addr) & 0xF0000000) + 0x02000000) \
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+((((UINT32)(addr)&0xFFFFF)<<5) \
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+((UINT32)(bit)<<2)))
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#define PCR_READ_4(pCtrl, addr) \
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vxbRead32 ((pCtrl->pcrHandle), \
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(UINT32 *)((char *)(pCtrl->pInst->pRegBase[0]) + (addr)))
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#define PCR_WRITE_4(pCtrl, addr, data) \
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vxbWrite32 ((pCtrl->pcrHandle), \
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(UINT32 *)((char *)(pCtrl->pInst->pRegBase[0]) + (addr)), data)
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#define GPIO_READ_4(pCtrl, addr) \
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vxbRead32 ((pCtrl->gpioHandle), \
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(UINT32 *)((char *)(pCtrl->pInst->pRegBase[1]) + (addr)))
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#define GPIO_WRITE_4(pCtrl, addr, data) \
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vxbWrite32 ((pCtrl->gpioHandle), \
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(UINT32 *)((char *)(pCtrl->pInst->pRegBase[1]) + (addr)), data)
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#define KINETIS_GPIO_BANK_WIDTH 32
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#define PORT_PCR 0x00
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#define PORT_GPCLR 0x80
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#define PORT_GPCHR 0x84
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#define PORT_ISFR 0xa0
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#define PORT_DFER 0xc0
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#define PORT_DFCR 0xc4
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#define PORT_DFWR 0xc8
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#define PCR_IRQC_MASK 0x000f0000
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#define PCR_MUX_MASK 0x00000700
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#define PCR_PULL_MASK 0x00000003
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#define KINETIS_GPIO_INPUT 0x0
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#define KINETIS_GPIO_OUTPUT 0x1
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#define KINETIS_GPIO_PULL_DISABLE 0x0
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#define KINETIS_GPIO_PULL_DOWN 0x2
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#define KINETIS_GPIO_PULL_UP 0x3
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#define KINETIS_GPIO_INT_DMA_DISABLE 0x0
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#define KINETIS_GPIO_DMA_RISING 0x1
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#define KINETIS_GPIO_DMA_FAILING 0x2
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#define KINETIS_GPIO_DMA_EITHER 0x3
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#define KINETIS_GPIO_INT_LEVEL_LOW 0x8
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#define KINETIS_GPIO_INT_RISING 0x9
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#define KINETIS_GPIO_INT_FAILING 0xa
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#define KINETIS_GPIO_INT_EITHER 0xb
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#define KINETIS_GPIO_INT_LEVEL_HIGH 0xc
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#define PDOR_ALIAS_OFFSET 0
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#define PSOR_ALIAS_OFFSET (0x04 << 5)
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#define PCOR_ALIAS_OFFSET (0x08 << 5)
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#define PTOR_ALIAS_OFFSET (0x0c << 5)
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#define PDIR_ALIAS_OFFSET (0x10 << 5)
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#define PDDR_ALIAS_OFFSET (0x14 << 5)
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/* Private context structure */
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typedef struct kinetisIsrEntry
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{
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VOIDFUNCPTR pIsr; /* ISR */
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void * pArg; /* parameter */
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} KINETIS_ISR_ENTRY;
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typedef struct kinetisGpioDrvCtrl
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{
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VXB_DEVICE_ID pInst; /* pointer to the controller instance */
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UINT32 validBmp; /* this is a valid bitmap for this controller.
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bit 0 means free, 1 means used. */
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void * pcrHandle; /* handle of PCR vxbRead/vxbWrite */
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void * gpioHandle; /* handle of GPIO vxbRead/vxbWrite */
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KINETIS_ISR_ENTRY isrTable[KINETIS_GPIO_BANK_WIDTH]; /* ISR handler table */
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/* allocate a pin. */
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STATUS (*gpioAlloc)
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(
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VXB_DEVICE_ID pDev,
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UINT32 pin
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);
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/* release a pin */
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STATUS (*gpioRelease)
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(
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VXB_DEVICE_ID pDev,
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UINT32 pin
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);
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/* get input value of a pin */
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UINT32 (*gpioInput)
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(
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VXB_DEVICE_ID pDev,
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UINT32 pin
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);
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/* output value to a pin */
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STATUS (*gpioOutput)
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(
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VXB_DEVICE_ID pDev,
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UINT32 pin,
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UINT32 value
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);
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/* config Gpio pin */
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STATUS (*gpioConfig)
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(
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VXB_DEVICE_ID pDev,
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UINT32 pin,
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UINT32 trigger, /* trigger mode */
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UINT32 pull, /* internal pull down or up */
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UINT32 dir /* input or output */
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);
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/* set ISR for a pin */
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STATUS (*gpioISRSet)
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(
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VXB_DEVICE_ID pDev,
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UINT32 pin,
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VOIDFUNCPTR pIsr, /* ISR */
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void * pArg /* parameter */
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);
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} KINETIS_GPIO_DRVCTRL;
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCvxbKinetisGpioh */
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